Simulation Results: hmac

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.83 %
  • code
  • 95.95 %
  • assert
  • 96.74 %
  • func
  • 28.78 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.000s 1837.851us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 138.799us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 61.700us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.000s 8147.677us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 992.307us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.000s 129.100us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 61.700us 1 1 100.00
hmac_csr_aliasing 3.000s 992.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 2.000s 28.405us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 3.000s 657.504us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 217.000s 95427.378us 1 1 100.00
hmac_test_sha384_vectors 22.000s 2662.602us 1 1 100.00
hmac_test_sha512_vectors 23.000s 604.473us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 310.929us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 1484.234us 1 1 100.00
hmac_test_hmac512_vectors 11.000s 1176.509us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.000s 1207.575us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 74.000s 3519.791us 1 1 100.00
error 1 1 100.00
hmac_error 60.000s 1882.582us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 11.000s 1284.031us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.000s 1837.851us 1 1 100.00
hmac_long_msg 2.000s 28.405us 1 1 100.00
hmac_back_pressure 3.000s 657.504us 1 1 100.00
hmac_datapath_stress 74.000s 3519.791us 1 1 100.00
hmac_burst_wr 12.000s 1207.575us 1 1 100.00
hmac_stress_all 580.000s 42173.939us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.000s 1837.851us 1 1 100.00
hmac_long_msg 2.000s 28.405us 1 1 100.00
hmac_back_pressure 3.000s 657.504us 1 1 100.00
hmac_datapath_stress 74.000s 3519.791us 1 1 100.00
hmac_wipe_secret 11.000s 1284.031us 1 1 100.00
hmac_test_sha256_vectors 217.000s 95427.378us 1 1 100.00
hmac_test_sha384_vectors 22.000s 2662.602us 1 1 100.00
hmac_test_sha512_vectors 23.000s 604.473us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 310.929us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 1484.234us 1 1 100.00
hmac_test_hmac512_vectors 11.000s 1176.509us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.000s 1837.851us 1 1 100.00
hmac_long_msg 2.000s 28.405us 1 1 100.00
hmac_back_pressure 3.000s 657.504us 1 1 100.00
hmac_datapath_stress 74.000s 3519.791us 1 1 100.00
hmac_burst_wr 12.000s 1207.575us 1 1 100.00
hmac_error 60.000s 1882.582us 1 1 100.00
hmac_wipe_secret 11.000s 1284.031us 1 1 100.00
hmac_test_sha256_vectors 217.000s 95427.378us 1 1 100.00
hmac_test_sha384_vectors 22.000s 2662.602us 1 1 100.00
hmac_test_sha512_vectors 23.000s 604.473us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 310.929us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 1484.234us 1 1 100.00
hmac_test_hmac512_vectors 11.000s 1176.509us 1 1 100.00
hmac_stress_all 580.000s 42173.939us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 580.000s 42173.939us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 22.921us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 96.967us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 399.696us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 399.696us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 138.799us 1 1 100.00
hmac_csr_rw 1.000s 61.700us 1 1 100.00
hmac_csr_aliasing 3.000s 992.307us 1 1 100.00
hmac_same_csr_outstanding 2.000s 52.214us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 138.799us 1 1 100.00
hmac_csr_rw 1.000s 61.700us 1 1 100.00
hmac_csr_aliasing 3.000s 992.307us 1 1 100.00
hmac_same_csr_outstanding 2.000s 52.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 91.438us 1 1 100.00
hmac_tl_intg_err 2.000s 133.774us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 133.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.000s 1837.851us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.000s 42.748us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 3.000s 50.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 72.386us 1 1 100.00