Simulation Results: lc_ctrl/volatile_unlock_disabled

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.89 %
  • code
  • 92.85 %
  • assert
  • 96.69 %
  • func
  • 86.13 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 87.34 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 62.969us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 18.154us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 25.441us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 115.638us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.767us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 58.685us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 25.441us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.767us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 125.320us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 2096.419us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 12.241us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.000s 35.522us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 298.235us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_ctrl_prog_failure 1.000s 35.522us 1 1 100.00
lc_ctrl_errors 4.000s 298.235us 1 1 100.00
lc_ctrl_security_escalation 3.000s 393.866us 1 1 100.00
lc_ctrl_jtag_state_failure 20.000s 6614.048us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 960.160us 1 1 100.00
lc_ctrl_jtag_errors 13.000s 1738.436us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 2932.413us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 819.073us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 960.160us 1 1 100.00
lc_ctrl_jtag_errors 13.000s 1738.436us 1 1 100.00
lc_ctrl_jtag_access 9.000s 1796.127us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 1348.486us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 864.344us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 76.325us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 21708.464us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 1089.885us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 203.074us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 273.348us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 208.050us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 2575.296us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 13.159us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 81.000s 17180.697us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 26.100us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 77.738us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 77.738us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 18.154us 1 1 100.00
lc_ctrl_csr_rw 1.000s 25.441us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.767us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 79.985us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 18.154us 1 1 100.00
lc_ctrl_csr_rw 1.000s 25.441us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.767us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 79.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 459.220us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 125.472us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 125.472us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 2096.419us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 459.220us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 459.220us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 459.220us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 459.220us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 459.220us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 459.220us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 459.220us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 1450.406us 1 1 100.00
lc_ctrl_sec_cm 3.000s 459.220us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.000s 393.866us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 125.320us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 819.073us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 1157.579us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 1157.579us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 240.797us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1612.999us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1612.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 26.000s 14287.104us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 101748423059120794644158153088184528710941802692032829963397861370117044615915 3428
UVM_INFO @ 14287104451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---