Simulation Results: lc_ctrl/volatile_unlock_enabled

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.62 %
  • code
  • 93.32 %
  • assert
  • 96.69 %
  • func
  • 84.84 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 87.68 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 22.326us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 12.591us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 34.210us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 59.190us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 37.712us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 192.790us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 34.210us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 37.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 86.505us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.000s 627.569us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 84.779us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 101.756us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 386.300us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_ctrl_prog_failure 2.000s 101.756us 1 1 100.00
lc_ctrl_errors 5.000s 386.300us 1 1 100.00
lc_ctrl_security_escalation 4.000s 410.098us 1 1 100.00
lc_ctrl_jtag_state_failure 15.000s 7913.922us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 1731.046us 1 1 100.00
lc_ctrl_jtag_errors 7.000s 4155.777us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 293.529us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 644.768us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 1731.046us 1 1 100.00
lc_ctrl_jtag_errors 7.000s 4155.777us 1 1 100.00
lc_ctrl_jtag_access 5.000s 7437.606us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 1078.291us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 200.323us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 85.919us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.000s 5536.755us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 325.109us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 492.087us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 118.331us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 43.649us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 817.273us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 16.645us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 50.000s 8917.207us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 14.811us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 104.520us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 104.520us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 12.591us 1 1 100.00
lc_ctrl_csr_rw 1.000s 34.210us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 37.712us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 38.736us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 12.591us 1 1 100.00
lc_ctrl_csr_rw 1.000s 34.210us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 37.712us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 38.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 108.850us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 250.309us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 250.309us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.000s 627.569us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_ctrl_sec_cm 2.000s 108.850us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_ctrl_sec_cm 2.000s 108.850us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_ctrl_sec_cm 2.000s 108.850us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_ctrl_sec_cm 2.000s 108.850us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_ctrl_sec_cm 2.000s 108.850us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_ctrl_sec_cm 2.000s 108.850us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_ctrl_sec_cm 2.000s 108.850us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 3.000s 1990.173us 1 1 100.00
lc_ctrl_sec_cm 2.000s 108.850us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 410.098us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 86.505us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 644.768us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 327.814us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 327.814us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 1284.742us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 816.097us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 816.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.000s 788.796us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 53065556819261986707910115363848395316336579672525706786900587300850041136472 843
UVM_INFO @ 788795955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---