Simulation Results: mbx

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.49 %
  • code
  • 89.12 %
  • assert
  • 97.72 %
  • func
  • 84.63 %
  • block
  • 96.69 %
  • line
  • 96.71 %
  • branch
  • 91.35 %
  • toggle
  • 79.31 %
Validation stages
V1
100.00%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 47.000s 5224.401us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 104.668us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 13.270us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 379.321us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 102.385us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 1.000s 106.004us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 13.270us 1 1 100.00
mbx_csr_aliasing 2.000s 102.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 36.000s 16700.577us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 4.000s 393.154us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 30.000s 6710.552us 1 1 100.00
mbx_doe_intr_msg 0 1 0.00
mbx_doe_intr_msg 3.000s 394.621us 0 1 0.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 29.990us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 45.930us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 3.228us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 3.228us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 104.668us 1 1 100.00
mbx_csr_rw 1.000s 13.270us 1 1 100.00
mbx_csr_aliasing 2.000s 102.385us 1 1 100.00
mbx_same_csr_outstanding 2.000s 67.673us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 104.668us 1 1 100.00
mbx_csr_rw 1.000s 13.270us 1 1 100.00
mbx_csr_aliasing 2.000s 102.385us 1 1 100.00
mbx_same_csr_outstanding 2.000s 67.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 95.400us 1 1 100.00
mbx_sec_cm 2.000s 27.251us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed 1 test run
mbx_stress_zero_delays 50985906110509377037160686645595581797383546937870326494763606252675418639903 144
UVM_ERROR @ 393153582 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 393153582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_doe_intr_msg_vseq.sv:56) [_item] Check failed act_data == data[i] (* [*] vs * [*]) DOE_INTR_MSG_DATA does not have the expected value 1 test run
mbx_doe_intr_msg 12710364702173069128405231843315230459568060491746249675039427472900786762666 83
UVM_INFO @ 394620868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
mbx_tl_errors 86345217203845169386946937609284170223746237788354743775885590065218830451511 85
TL item was: req: (cip_tl_seq_item@17847) { a_addr: 'hda1fb030 a_data: 'h2b599cce a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'h38 a_opcode: 'h0 a_user: 'h26c27 d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3228300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---