Simulation Results: otp_ctrl

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.06 %
  • code
  • 72.56 %
  • assert
  • 94.13 %
  • func
  • 55.49 %
  • line
  • 87.58 %
  • branch
  • 84.19 %
  • cond
  • 85.55 %
  • toggle
  • 68.06 %
  • FSM
  • 37.40 %
Validation stages
V1
100.00%
V2
70.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.160s 59.706us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 2.650s 272.165us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.240s 81.689us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.770s 107.108us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.500s 603.707us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 10.460s 6087.630us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.520s 1242.238us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.770s 107.108us 1 1 100.00
otp_ctrl_csr_aliasing 10.460s 6087.630us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.500s 170.815us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.460s 150.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 108.620s 8255.251us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.530s 136.397us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 15.770s 7077.316us 0 1 0.00
otp_ctrl_check_fail 5.770s 414.562us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 9.100s 1257.311us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 17.050s 1316.720us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 2.600s 122.846us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.070s 4972.808us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 8.690s 288.471us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 15.470s 1174.979us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 3.570s 199.871us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 21.460s 2833.234us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.570s 45.246us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.020s 75.373us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.010s 127.234us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.010s 127.234us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.240s 81.689us 1 1 100.00
otp_ctrl_csr_rw 1.770s 107.108us 1 1 100.00
otp_ctrl_csr_aliasing 10.460s 6087.630us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.940s 1608.634us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.240s 81.689us 1 1 100.00
otp_ctrl_csr_rw 1.770s 107.108us 1 1 100.00
otp_ctrl_csr_aliasing 10.460s 6087.630us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.940s 1608.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
otp_ctrl_tl_intg_err 11.520s 12285.325us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.520s 12285.325us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 2.650s 272.165us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 2.650s 272.165us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
otp_ctrl_macro_errs 15.470s 1174.979us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
otp_ctrl_macro_errs 15.470s 1174.979us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.010s 151.913us 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.530s 136.397us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.770s 414.562us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 17.050s 1316.720us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 17.050s 1316.720us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 17.050s 1316.720us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 17.050s 1316.720us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 17.050s 1316.720us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 2.650s 272.165us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 17.050s 1316.720us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 2.650s 272.165us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 264.210s 15380.102us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 9.100s 1257.311us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 2.650s 272.165us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 2.650s 272.165us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 15.470s 1174.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 62.810s 26642.037us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 4.940s 512.009us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 2 test runs
otp_ctrl_background_chks 37717316978725301920168104889492462711265520482414639867638355045721975643701 10989
UVM_INFO @ 7077315987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 22630941805157386832965867178111045906963631908691029380873178828988248096442 18596
UVM_INFO @ 2833234144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_parallel_key_req 102203548820898463849928467878209794568636991160172119477914352726848721647913 1708
UVM_INFO @ 122845977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 35284494549809074022207938022604010141146600775325319494709925393739056976313 2518
UVM_INFO @ 199871067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 14506326151205040068355313176739825180946932528423493822061040164586986991661 110067
UVM_INFO @ 8255250579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 48840814237519088469404389952242804903519735935909300850466108132774413232375 89
UVM_INFO @ 26642036824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 79815956497603562644905904245703130468371769985714677375102782458925339324634 4159
UVM_INFO @ 414562405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 42566574939329528906605380335705688352589795589958061764787698893883989608854 551
UVM_INFO @ 512008985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---