Simulation Results: rom_ctrl/32kb

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.73 %
  • code
  • 83.19 %
  • assert
  • 97.38 %
  • func
  • 97.62 %
  • block
  • 86.94 %
  • line
  • 86.21 %
  • branch
  • 86.11 %
  • toggle
  • 84.27 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 2.000s 335.588us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 58.960us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 78.794us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 145.768us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 1.000s 107.070us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 57.154us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 78.794us 1 1 100.00
rom_ctrl_csr_aliasing 1.000s 107.070us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 57.349us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 51.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 164.093us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 3.000s 102.339us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 379.706us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 59.567us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 2.000s 238.285us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 2.000s 238.285us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 58.960us 1 1 100.00
rom_ctrl_csr_rw 3.000s 78.794us 1 1 100.00
rom_ctrl_csr_aliasing 1.000s 107.070us 1 1 100.00
rom_ctrl_same_csr_outstanding 1.000s 141.830us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 58.960us 1 1 100.00
rom_ctrl_csr_rw 3.000s 78.794us 1 1 100.00
rom_ctrl_csr_aliasing 1.000s 107.070us 1 1 100.00
rom_ctrl_same_csr_outstanding 1.000s 141.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 164.001us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 49.000s 234.752us 1 1 100.00
rom_ctrl_tl_intg_err 21.000s 182.432us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 49.000s 234.752us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 49.000s 234.752us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 49.000s 234.752us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 49.000s 234.752us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 2.000s 335.588us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 2.000s 335.588us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 2.000s 335.588us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 21.000s 182.432us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
rom_ctrl_kmac_err_chk 3.000s 379.706us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 22.652us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 164.001us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 49.000s 234.752us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 28.000s 5159.513us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 83032382794428208555943117791444598010519919811669154646491384490032667763367 88
UVM_INFO @ 164092551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:295) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.compare_vif.is_waiting()) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 32135561981267559045946612628089920842372651695859526766186538383873557925369 87
UVM_INFO @ 22652331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---