Simulation Results: rom_ctrl/64kb

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.25 %
  • code
  • 83.19 %
  • assert
  • 96.65 %
  • func
  • 96.91 %
  • block
  • 86.94 %
  • line
  • 86.21 %
  • branch
  • 86.11 %
  • toggle
  • 84.27 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 745.870us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 55.109us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 91.873us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 80.324us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 63.954us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 177.842us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 91.873us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 63.954us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 56.364us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 51.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 15.520us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.000s 135.826us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 4.000s 62.277us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 52.080us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 199.676us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 199.676us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 55.109us 1 1 100.00
rom_ctrl_csr_rw 3.000s 91.873us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 63.954us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 71.333us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 55.109us 1 1 100.00
rom_ctrl_csr_rw 3.000s 91.873us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 63.954us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 71.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 167.323us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 96.000s 559.925us 1 1 100.00
rom_ctrl_tl_intg_err 22.000s 238.551us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 96.000s 559.925us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 96.000s 559.925us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 96.000s 559.925us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 96.000s 559.925us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 745.870us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 745.870us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 745.870us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 22.000s 238.551us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
rom_ctrl_kmac_err_chk 4.000s 62.277us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1468.000s 1000000.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 167.323us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 96.000s 559.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 36.000s 14550.800us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 87501875116337491084506402319039519054308123476469269670743254220921465722330 88
UVM_INFO @ 15520292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rom_ctrl_corrupt_sig_fatal_chk 81651748467582151759333423980079438622554778150093209581367375566197661098238 92
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---