Simulation Results

Simulation Results: rv_dm/use_dmi_interface

30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.65 %

code
74.17 %

assert
96.59 %

func
92.19 %

block
89.80 %

line
89.78 %

branch
72.32 %

toggle
72.08 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	31.000s	861.031us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	31.000s	805.488us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	147.841us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	34.000s	32682.190us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	34.000s	1592.025us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	34.000s	3000.573us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	31.000s	1291.818us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	78.000s	51479.790us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	57.000s	76007.257us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	301.750us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	32.000s	614.167us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	33.000s	149.836us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	30.000s	105.564us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	30.000s	174.272us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	32.000s	971.068us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	32.000s	253.230us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	30.000s	406.908us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	301.750us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	31.000s	254.420us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	32.000s	269.767us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	33.000s	149.836us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	30.000s	64.826us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	33.000s	225.865us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	32.000s	191.540us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	70.000s	8308.507us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	62.000s	19428.978us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	32.000s	77.676us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	62.000s	19428.978us	1	1	100.00
	rv_dm_csr_rw	32.000s	191.540us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	32.000s	97.328us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	36.000s	140.079us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	31.000s	861.031us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	33.000s	539.282us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	32.000s	98.354us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	33.000s	390.154us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	31.000s	1538.882us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	35.000s	5960.093us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	30.000s	403.526us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	31.000s	474.909us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	31.000s	189.474us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	38.000s	541.360us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	32.000s	1862.695us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	31.000s	236.074us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	30.000s	368.195us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	34.000s	7321.636us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	88.000s	8649.231us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	263.715us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	7370.000s	10000000.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	31.000s	128.761us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	31.000s	272.760us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	31.000s	272.760us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	62.000s	19428.978us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	225.865us	1	1	100.00
	rv_dm_csr_rw	32.000s	191.540us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	962.112us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	62.000s	19428.978us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	225.865us	1	1	100.00
	rv_dm_csr_rw	32.000s	191.540us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	962.112us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	33.000s	1825.841us	1	1	100.00
	rv_dm_tl_intg_err	36.000s	4458.675us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	36.000s	4458.675us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	1862.695us	1	1	100.00
	rv_dm_debug_disabled	30.000s	114.335us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	1862.695us	1	1	100.00
	rv_dm_debug_disabled	30.000s	114.335us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	31.000s	861.031us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	32.000s	203.090us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	78.691us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	78.691us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	32.000s	203.090us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	34.000s	323.960us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	133.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				3 test runs
	rv_dm_delayed_resp_sba_tl_access	79046894731876546963705503857268296185385563582666583495751185296480193237389	107	UVM_INFO @ 403525898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	25049173531103164206897625059074252547933132404639645890650804425878578694582	107	UVM_INFO @ 474909213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	93160723762606077282335614631595614390653456553268993607400090508467236438700	107	UVM_INFO @ 189473916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	81725387504586064197409655788790946445692029595777731660374252602720334190228	87	UVM_INFO @ 368195378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	29808101603729524272426466575079133334622445842346773599548996293677184523393	98	UVM_INFO @ 323960384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	43687545293159547446410598397534991113323451071435124695560053380364134355014	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	105323995254408206538818759099069047024497667187327171880714755115371492295873	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				1 test run
	rv_dm_sba_tl_access	76180340386335062466046571709677320437350687137456593721768959310771998385465	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23803
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	26268053292560832282746967876937701746288900209550204386019009596560479612415	87	UVM_INFO @ 105564318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	74385856967284439954969512776141085600897912396636056509901427780986857509174	87	UVM_INFO @ 541359884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---