Simulation Results: rv_timer

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.83 %
  • code
  • 90.45 %
  • assert
  • 97.47 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 120.893us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 20.674us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 13.944us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 322.460us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 31.537us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 17.391us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 13.944us 1 1 100.00
rv_timer_csr_aliasing 1.000s 31.537us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 531.127us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 2605.979us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 11.000s 33764.772us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 11.000s 33764.772us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.000s 29.916us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 44.290us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 13.014us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.000s 88.913us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.000s 88.913us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 20.674us 1 1 100.00
rv_timer_csr_rw 1.000s 13.944us 1 1 100.00
rv_timer_csr_aliasing 1.000s 31.537us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 41.835us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 20.674us 1 1 100.00
rv_timer_csr_rw 1.000s 13.944us 1 1 100.00
rv_timer_csr_aliasing 1.000s 31.537us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 41.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 138.708us 1 1 100.00
rv_timer_tl_intg_err 1.000s 139.746us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 139.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 125.620us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 631.525us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 21.000s 15050.961us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 101196038894071322639388442301950962039080681496495270124336104749634624270435 86
UVM_INFO @ 125620142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 33444042699703888851502215549397868555037117472849638823525308625483375935960 84
UVM_INFO @ 531126518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 114709461754877674739423243980787920283897839153994808754108157846102717632083 84
UVM_INFO @ 631524731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---