Simulation Results: spi_device/1r1w

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.74 %
  • code
  • 89.24 %
  • assert
  • 95.40 %
  • func
  • 69.58 %
  • block
  • 98.32 %
  • line
  • 98.72 %
  • branch
  • 96.95 %
  • toggle
  • 72.75 %
  • FSM
  • 88.54 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 62.000s 2442.938us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 47.526us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 142.482us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 38.000s 15268.734us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 8.000s 206.374us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 28.601us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 142.482us 1 1 100.00
spi_device_csr_aliasing 8.000s 206.374us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 12.461us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 25.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 58.763us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 1.365us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 5.247us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 28.163us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 28.163us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.000s 14.768us 1 1 100.00
spi_device_tpm_sts_read 2.000s 62.414us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 23.000s 3457.975us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 17.000s 2561.428us 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 82.536us 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 82.536us 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 12.000s 1044.455us 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 12.000s 1044.455us 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 12.000s 1044.455us 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 12.000s 1044.455us 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 12.000s 1044.455us 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 25.000s 23599.013us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 12.000s 884.997us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 12.000s 884.997us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 12.000s 884.997us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 21.000s 1275.976us 1 1 100.00
spi_device_read_buffer_direct 6.000s 1112.967us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 12.000s 884.997us 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 52.000s 12130.630us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.000s 240.505us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.000s 240.505us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 113.000s 35205.161us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 62.000s 2442.938us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 107.000s 34502.655us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 303.000s 55928.582us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 29.287us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 21.416us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.000s 112.051us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.000s 112.051us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 47.526us 1 1 100.00
spi_device_csr_rw 3.000s 142.482us 1 1 100.00
spi_device_csr_aliasing 8.000s 206.374us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 333.864us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 47.526us 1 1 100.00
spi_device_csr_rw 3.000s 142.482us 1 1 100.00
spi_device_csr_aliasing 8.000s 206.374us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 333.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 194.430us 1 1 100.00
spi_device_tl_intg_err 8.000s 201.995us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.000s 201.995us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 33438541255229827846803020481320070241261088562514052626321654538336860979101 87
UVM_ERROR @ 964605 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[976] not found within the scope .
UVM_ERROR @ 964605 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[976] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 109156980007971321232123365121238312409159134796834780109514130131501425012639 85
UVM_ERROR @ 2397898 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1a2 [110100010] vs 0x0 [0])
UVM_ERROR @ 2408898 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x332 [1100110010] vs 0x0 [0])
UVM_ERROR @ 2449898 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x18 [11000] vs 0x0 [0])
UVM_ERROR @ 2460898 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x127 [100100111] vs 0x0 [0])