Simulation Results: sram_ctrl/main

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.34 %
  • code
  • 95.67 %
  • assert
  • 97.55 %
  • func
  • 92.80 %
  • block
  • 96.02 %
  • line
  • 96.67 %
  • branch
  • 94.16 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 2817.153us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 32.550us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.970us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 884.943us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 61.633us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 725.426us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 17.970us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 61.633us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 214.000s 23165.386us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 70.000s 5725.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 20.000s 18221.226us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 112.000s 15235.745us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 117.000s 8890.575us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 25.000s 6068.424us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 9.000s 9726.969us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 6303.988us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 1344.074us 1 1 100.00
sram_ctrl_partial_access_b2b 187.000s 45939.874us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 3649.270us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 708.917us 0 1 0.00
sram_ctrl_throughput_w_readback 3.000s 696.715us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 719.493us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 5.000s 347.190us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 238.000s 38062.573us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 97.767us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 296.761us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 296.761us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 32.550us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.970us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 61.633us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 20.410us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 32.550us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.970us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 61.633us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 20.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 9018.983us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 655.366us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 290.504us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 655.366us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 290.504us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 719.493us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 719.493us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.970us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 6303.988us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 6303.988us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 6303.988us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 9.000s 9726.969us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 6.000s 3171.213us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 9018.983us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 700.421us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2817.153us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2817.153us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 6303.988us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 655.366us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 9.000s 9726.969us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 655.366us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 655.366us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 2817.153us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 655.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.000s 519.762us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 74455436528199663960792801325618987423536333747876515978407227489846973674370 86
UVM_INFO @ 3649269767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 53368721449682448276767681794300692791398574355921088403599739991081296738736 86
UVM_INFO @ 708917021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 7860602443296221134331316137471096089297205945340018014764847055945739728252 86
UVM_INFO @ 696715183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---