Simulation Results: sram_ctrl/ret

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.22 %
  • code
  • 81.12 %
  • assert
  • 97.53 %
  • func
  • 89.00 %
  • block
  • 92.25 %
  • line
  • 93.03 %
  • branch
  • 86.50 %
  • toggle
  • 78.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 157.885us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 94.249us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.309us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 65.271us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.370us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 62.093us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 16.309us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.370us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 807.119us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 348.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 899.056us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 144.000s 2901.465us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 1918.870us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 13.000s 561.394us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 932.367us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 10.000s 998.921us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 107.453us 1 1 100.00
sram_ctrl_partial_access_b2b 109.000s 6842.788us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 189.494us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 23.288us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 113.360us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 251.913us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 89.443us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 25.000s 2855.117us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 38.656us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 97.090us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 97.090us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 94.249us 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.309us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.370us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 37.612us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 94.249us 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.309us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.370us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 37.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 218.313us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 6531.745us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 330.392us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 6531.745us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 330.392us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 251.913us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 251.913us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.309us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 10.000s 998.921us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 998.921us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 998.921us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 932.367us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 272.672us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 218.313us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 36.442us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 157.885us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 157.885us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 10.000s 998.921us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 6531.745us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 932.367us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 6531.745us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 6531.745us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 157.885us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 6531.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
sram_ctrl_stress_all_with_rand_reset 5.000s 603.852us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 94102866603399335970027053993668204604542828623517612914409624681299624502084 86
UVM_INFO @ 189494462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 59177229860950516054190073389706852131138083904426776237358031716614445154299 86
UVM_INFO @ 23287586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 19205154007325831779944622289913325877805759110085741118187734773907438432109 86
UVM_INFO @ 113359522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 24085473215396338552904466194611027014866770197977819370470067175336783494545 119
UVM_INFO @ 603852018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---