Simulation Results: uart

 
30/07/2026 19:40:39 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.20 %
  • code
  • 96.65 %
  • assert
  • 98.27 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 88.74 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 8.000s 6268.820us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 2.000s 31.248us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 2.000s 242.535us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 572.140us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 3.000s 19.863us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 7.000s 26.065us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 2.000s 242.535us 1 1 100.00
uart_csr_aliasing 3.000s 19.863us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 41.000s 159904.990us 1 1 100.00
parity 2 2 100.00
uart_smoke 8.000s 6268.820us 1 1 100.00
uart_tx_rx 41.000s 159904.990us 1 1 100.00
parity_error 2 2 100.00
uart_intr 47.000s 43823.610us 1 1 100.00
uart_rx_parity_err 182.000s 160463.107us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 41.000s 159904.990us 1 1 100.00
uart_intr 47.000s 43823.610us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 349.000s 173712.659us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 8.000s 34673.537us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 14.000s 19867.949us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 47.000s 43823.610us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 47.000s 43823.610us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 47.000s 43823.610us 1 1 100.00
perf 1 1 100.00
uart_perf 50.000s 8901.041us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.000s 5606.027us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.000s 5606.027us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.000s 934.392us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 8.000s 4857.485us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 13.000s 6674.053us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 39.000s 7495.612us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 852.000s 120096.040us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 57.000s 106762.000us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 21.325us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 24.770us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 47.702us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 47.702us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 2.000s 31.248us 1 1 100.00
uart_csr_rw 2.000s 242.535us 1 1 100.00
uart_csr_aliasing 3.000s 19.863us 1 1 100.00
uart_same_csr_outstanding 2.000s 16.095us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 2.000s 31.248us 1 1 100.00
uart_csr_rw 2.000s 242.535us 1 1 100.00
uart_csr_aliasing 3.000s 19.863us 1 1 100.00
uart_same_csr_outstanding 2.000s 16.095us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 181.395us 1 1 100.00
uart_tl_intg_err 2.000s 57.801us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 57.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 45.000s 5280.631us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 47947594918435057896357823745114535144642944984971013799017028428402766837815 83
UVM_ERROR @ 71798076 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 71825103 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 132473691 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 132473691 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0