Simulation Results: ac_range_check

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.37 %
  • code
  • 92.97 %
  • assert
  • 97.75 %
  • func
  • 56.40 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.73 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 24.000s 2867.255us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 34.000s 5902.346us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 144.174us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 1.000s 71.586us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 32.000s 12705.636us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 13.000s 346.896us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 1.000s 77.709us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 1.000s 71.586us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 346.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 21.866us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 19.000s 889.591us 1 1 100.00
stress_all 0 1 0.00
ac_range_check_stress_all 90.000s 100570.689us 0 1 0.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 132.658us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 15.048us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 311.716us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 311.716us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 144.174us 1 1 100.00
ac_range_check_csr_rw 1.000s 71.586us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 346.896us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 56.303us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 144.174us 1 1 100.00
ac_range_check_csr_rw 1.000s 71.586us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 346.896us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 56.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 405.121us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 405.121us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 405.121us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 405.121us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 53.000s 2983.694us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 15.648us 1 1 100.00
ac_range_check_tl_intg_err 6.000s 230.657us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 241.000s 1744.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 19.000s 1916.550us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:166) [scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo. 1 test run
ac_range_check_stress_all 13122881397981089656279352141042555286074205430490762999196803528347232944716 12828
UVM_INFO @ 100570689308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---