Simulation Results: aes/gcm_masked

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.78 %
  • code
  • 95.16 %
  • assert
  • 98.43 %
  • func
  • 63.76 %
  • block
  • 95.81 %
  • line
  • 97.52 %
  • branch
  • 89.60 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
89.47%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 170.915us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 159.997us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 64.484us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 67.637us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 2070.446us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 130.510us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 55.373us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 67.637us 1 1 100.00
aes_csr_aliasing 2.000s 130.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 159.997us 1 1 100.00
aes_config_error 4.000s 194.557us 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 159.997us 1 1 100.00
aes_config_error 4.000s 194.557us 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 142.055us 1 1 100.00
aes_b2b 4.000s 138.889us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 159.997us 1 1 100.00
aes_config_error 4.000s 194.557us 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
aes_alert_reset 3.000s 80.131us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 82.307us 1 1 100.00
aes_config_error 4.000s 194.557us 1 1 100.00
aes_alert_reset 3.000s 80.131us 1 1 100.00
trigger_clear_test 0 1 0.00
aes_clear 3.000s 184.082us 0 1 0.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 1859.527us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 1093.386us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 80.131us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 142.055us 1 1 100.00
aes_sideload 3.000s 89.980us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 167.597us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 2.000s 178.150us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 400.548us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 79.272us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 70.980us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 70.980us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.484us 1 1 100.00
aes_csr_rw 1.000s 67.637us 1 1 100.00
aes_csr_aliasing 2.000s 130.510us 1 1 100.00
aes_same_csr_outstanding 3.000s 242.702us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.484us 1 1 100.00
aes_csr_rw 1.000s 67.637us 1 1 100.00
aes_csr_aliasing 2.000s 130.510us 1 1 100.00
aes_same_csr_outstanding 3.000s 242.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 180.636us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3602.058s 0.000us 0 1 0.00
aes_control_fi 2.000s 89.473us 1 1 100.00
aes_cipher_fi 2.000s 64.426us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 618.401us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 618.401us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 618.401us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 618.401us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 118.541us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 854.878us 1 1 100.00
aes_tl_intg_err 2.000s 167.689us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 167.689us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 80.131us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 618.401us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 618.401us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 159.997us 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
aes_alert_reset 3.000s 80.131us 1 1 100.00
aes_core_fi 3.000s 532.541us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 400.548us 1 1 100.00
aes_config_error 4.000s 194.557us 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
aes_core_fi 3.000s 532.541us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 618.401us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 57.583us 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 142.055us 1 1 100.00
aes_sideload 3.000s 89.980us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 57.583us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 57.583us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 57.583us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 57.583us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 57.583us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 142.055us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3602.058s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3602.058s 0.000us 0 1 0.00
aes_control_fi 2.000s 89.473us 1 1 100.00
aes_cipher_fi 2.000s 64.426us 1 1 100.00
aes_ctr_fi 3.000s 159.915us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3602.058s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3602.058s 0.000us 0 1 0.00
aes_control_fi 2.000s 89.473us 1 1 100.00
aes_cipher_fi 2.000s 64.426us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 64.426us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3602.058s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3602.058s 0.000us 0 1 0.00
aes_control_fi 2.000s 89.473us 1 1 100.00
aes_ctr_fi 3.000s 159.915us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3602.058s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3602.058s 0.000us 0 1 0.00
aes_control_fi 2.000s 89.473us 1 1 100.00
aes_cipher_fi 2.000s 64.426us 1 1 100.00
aes_ctr_fi 3.000s 159.915us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 80.131us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3602.058s 0.000us 0 1 0.00
aes_control_fi 2.000s 89.473us 1 1 100.00
aes_cipher_fi 2.000s 64.426us 1 1 100.00
aes_ctr_fi 3.000s 159.915us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3602.058s 0.000us 0 1 0.00
aes_control_fi 2.000s 89.473us 1 1 100.00
aes_cipher_fi 2.000s 64.426us 1 1 100.00
aes_ctr_fi 3.000s 159.915us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3602.058s 0.000us 0 1 0.00
aes_control_fi 2.000s 89.473us 1 1 100.00
aes_ctr_fi 3.000s 159.915us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 54.027us 1 1 100.00
aes_fi 3602.058s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3602.058s 0.000us 0 1 0.00
aes_control_fi 2.000s 89.473us 1 1 100.00
aes_cipher_fi 2.000s 64.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 34.000s 1862.992us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_clear 5177959785320563807944491063269743455719277079017560078445916074987132966780 2297
TEST FAILED MESSAGES DID NOT MATCH
0 55 29 37 0
1 00 e9 70 0
Job timed out after * minutes 1 test run
aes_fi 38878448836663344389804584184165729188029130163249285783032332281836247616625 None
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
aes_stress_all 55129592485543063254393949031297394233078197498720970161658237344177447170135 593
UVM_INFO @ 178149605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 13838906336767765977089840946611353786757350566909175270481949248355195891239 310
UVM_INFO @ 1862992475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---