Simulation Results: aes/gcm_unmasked

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.16 %
  • code
  • 91.46 %
  • assert
  • 97.75 %
  • func
  • 63.27 %
  • block
  • 91.18 %
  • line
  • 92.97 %
  • branch
  • 84.09 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 76.821us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 108.040us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 87.240us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 65.667us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 9.000s 3051.796us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 91.281us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 115.026us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 65.667us 1 1 100.00
aes_csr_aliasing 3.000s 91.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 108.040us 1 1 100.00
aes_config_error 2.000s 97.228us 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 108.040us 1 1 100.00
aes_config_error 2.000s 97.228us 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 126.872us 1 1 100.00
aes_b2b 4.000s 189.432us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 108.040us 1 1 100.00
aes_config_error 2.000s 97.228us 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
aes_alert_reset 1.000s 98.684us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 55.209us 1 1 100.00
aes_config_error 2.000s 97.228us 1 1 100.00
aes_alert_reset 1.000s 98.684us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 77.686us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 1417.811us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 1.000s 98.684us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 126.872us 1 1 100.00
aes_sideload 2.000s 323.662us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 915.054us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 3.000s 1510.078us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 80.274us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 281.630us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 281.630us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 87.240us 1 1 100.00
aes_csr_rw 2.000s 65.667us 1 1 100.00
aes_csr_aliasing 3.000s 91.281us 1 1 100.00
aes_same_csr_outstanding 1.000s 63.690us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 87.240us 1 1 100.00
aes_csr_rw 2.000s 65.667us 1 1 100.00
aes_csr_aliasing 3.000s 91.281us 1 1 100.00
aes_same_csr_outstanding 1.000s 63.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 228.970us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 36.517us 0 1 0.00
aes_control_fi 2.000s 46.150us 1 1 100.00
aes_cipher_fi 2.000s 65.792us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 950.653us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 950.653us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 950.653us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 950.653us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 119.322us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1549.295us 1 1 100.00
aes_tl_intg_err 2.000s 101.253us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 101.253us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 1.000s 98.684us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 950.653us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 950.653us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 108.040us 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
aes_alert_reset 1.000s 98.684us 1 1 100.00
aes_core_fi 2.000s 134.808us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 97.228us 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
aes_core_fi 2.000s 134.808us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 950.653us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 64.636us 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 126.872us 1 1 100.00
aes_sideload 2.000s 323.662us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 64.636us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 64.636us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 64.636us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 64.636us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 64.636us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 126.872us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 36.517us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 36.517us 0 1 0.00
aes_control_fi 2.000s 46.150us 1 1 100.00
aes_cipher_fi 2.000s 65.792us 1 1 100.00
aes_ctr_fi 1.000s 56.280us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 36.517us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 36.517us 0 1 0.00
aes_control_fi 2.000s 46.150us 1 1 100.00
aes_cipher_fi 2.000s 65.792us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 65.792us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 36.517us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 36.517us 0 1 0.00
aes_control_fi 2.000s 46.150us 1 1 100.00
aes_ctr_fi 1.000s 56.280us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 36.517us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 36.517us 0 1 0.00
aes_control_fi 2.000s 46.150us 1 1 100.00
aes_cipher_fi 2.000s 65.792us 1 1 100.00
aes_ctr_fi 1.000s 56.280us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 1.000s 98.684us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 36.517us 0 1 0.00
aes_control_fi 2.000s 46.150us 1 1 100.00
aes_cipher_fi 2.000s 65.792us 1 1 100.00
aes_ctr_fi 1.000s 56.280us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 36.517us 0 1 0.00
aes_control_fi 2.000s 46.150us 1 1 100.00
aes_cipher_fi 2.000s 65.792us 1 1 100.00
aes_ctr_fi 1.000s 56.280us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 36.517us 0 1 0.00
aes_control_fi 2.000s 46.150us 1 1 100.00
aes_ctr_fi 1.000s 56.280us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 36.517us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 36.517us 0 1 0.00
aes_control_fi 2.000s 46.150us 1 1 100.00
aes_cipher_fi 2.000s 65.792us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 412.406us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_fi_vseq.sv:95) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset 1 test run
aes_fi 47727733224360015735414087323772408478242201796189275998936294870093358549703 9114
UVM_INFO @ 36517340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 343717283355038617173988242074978627143779264086864797762624034458507565238 264
UVM_INFO @ 412405952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---