Simulation Results: alert_handler

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.81 %
  • code
  • 92.12 %
  • assert
  • 98.29 %
  • func
  • 82.01 %
  • line
  • 99.73 %
  • branch
  • 98.61 %
  • cond
  • 92.37 %
  • toggle
  • 92.46 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 37.440s 2319.470us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.400s 603.901us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.260s 559.634us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 263.170s 28807.829us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 100.050s 1226.363us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.620s 296.470us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.260s 559.634us 1 1 100.00
alert_handler_csr_aliasing 100.050s 1226.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 221.500s 22611.659us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 21.980s 949.445us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1960.520s 177601.591us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 24.830s 725.657us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 37.440s 2319.470us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 21.200s 361.603us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 35.740s 915.641us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 221.160s 30707.539us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 758.650s 13184.599us 1 1 100.00
alert_handler_lpg_stub_clk 1417.980s 26739.596us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 3489.170s 371760.511us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.880s 180.749us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.480s 37.096us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.230s 19.391us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 19.120s 409.388us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 19.120s 409.388us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.400s 603.901us 1 1 100.00
alert_handler_csr_rw 7.260s 559.634us 1 1 100.00
alert_handler_csr_aliasing 100.050s 1226.363us 1 1 100.00
alert_handler_same_csr_outstanding 41.780s 3308.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.400s 603.901us 1 1 100.00
alert_handler_csr_rw 7.260s 559.634us 1 1 100.00
alert_handler_csr_aliasing 100.050s 1226.363us 1 1 100.00
alert_handler_same_csr_outstanding 41.780s 3308.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 153.310s 7165.284us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 153.310s 7165.284us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 153.310s 7165.284us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 153.310s 7165.284us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 491.420s 12630.724us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
alert_handler_tl_intg_err 4.100s 44.274us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 4.100s 44.274us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 153.310s 7165.284us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 37.440s 2319.470us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 37.440s 2319.470us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 37.440s 2319.470us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 37.440s 2319.470us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.830s 725.657us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 758.650s 13184.599us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.830s 725.657us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1960.520s 177601.591us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1960.520s 177601.591us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 22.040s 8953.571us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 36.040s 2919.720us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 54423024184612921931255103189724202360205002367791030695230789406450931390715 196
UVM_INFO @ 180749305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 13025433166571576834824595188943124538476636106933496196068058104651957819257 114
UVM_INFO @ 2919720071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---