| V1 |
|
27.27% |
| V2 |
|
32.16% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| unmapped |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_uart_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 9.313s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rx_overflow | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 9.313s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rand_baudrate | 0 | 1 | 0.00 | |||
| chip_sw_uart_rand_baudrate | 27.200s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 27.680s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_out | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 334.370s | 285.900us | 1 | 1 | 100.00 | |
| chip_sw_gpio_in | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 334.370s | 285.900us | 1 | 1 | 100.00 | |
| chip_sw_gpio_irq | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 334.370s | 285.900us | 1 | 1 | 100.00 | |
| chip_sw_example_tests | 1 | 4 | 25.00 | |||
| chip_sw_example_rom | 36.710s | 10.120us | 0 | 1 | 0.00 | |
| chip_sw_example_manufacturer | 15.401s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_concurrency | 223.160s | 168.819us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest_signed | 14.739s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| chip_csr_bit_bash | 8.840s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 8.860s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 8.860s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke | 1 | 1 | 100.00 | |||
| xbar_smoke | 9.750s | 11.902us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_spi_device_flash_mode | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 62.561s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through | 1 | 1 | 100.00 | |||
| chip_sw_spi_device_pass_through | 2136.920s | 3768.299us | 1 | 1 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 309.820s | 273.729us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_tpm | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_tpm | 17.026s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_spi_host_tx_rx | 21.610s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_host_tx_rx | 11.894s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_device_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_device_tx_rx | 10.112s | 0.000us | 0 | 1 | 0.00 | |
| chip_pin_mux | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 2.710s | 0.000us | 0 | 1 | 0.00 | |
| chip_padctrl_attributes | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 2.710s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_wake | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_wake | 12.467s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_retention | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_retention | 17.374s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 9.197s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_instruction_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 9.197s | 0.000us | 0 | 1 | 0.00 | |
| chip_jtag_csr_rw | 0 | 1 | 0.00 | |||
| chip_jtag_csr_rw | 111.490s | 132.603us | 0 | 1 | 0.00 | |
| chip_jtag_mem_access | 0 | 1 | 0.00 | |||
| chip_jtag_mem_access | 105.720s | 132.270us | 0 | 1 | 0.00 | |
| chip_rv_dm_ndm_reset_req | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 347.390s | 310.099us | 1 | 1 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 10.157s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 12.435s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0 | 1 | 0.00 | |||
| chip_rv_dm_lc_disabled | 96.970s | 129.400us | 0 | 1 | 0.00 | |
| chip_sw_timer | 1 | 1 | 100.00 | |||
| chip_sw_rv_timer_irq | 301.660s | 266.894us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 499.090s | 549.306us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 499.090s | 549.306us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 407.470s | 386.535us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 228.210s | 182.415us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 228.210s | 182.415us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 367.430s | 2310.339us | 1 | 1 | 100.00 | |
| chip_sw_plic_sw_irq | 1 | 1 | 100.00 | |||
| chip_sw_plic_sw_irq | 203.290s | 164.212us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 4 | 4 | 100.00 | |||
| chip_sw_otbn_randomness | 310.800s | 245.046us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 196.240s | 165.835us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_idle | 220.580s | 178.117us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 189.820s | 164.141us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_off_trans | 0 | 4 | 0.00 | |||
| chip_sw_clkmgr_off_aes_trans | 209.320s | 185.280us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_hmac_trans | 230.300s | 185.200us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_kmac_trans | 228.800s | 185.312us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_otbn_trans | 205.720s | 185.280us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 1 | 7 | 14.29 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 40.130s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 40.960s | 10.200us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 43.910s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 39.720s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 44.140s | 10.400us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.177s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 215.630s | 161.169us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_extended_range | 1 | 8 | 12.50 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 442.840s | 1962.707us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 39.690s | 10.220us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 41.860s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 47.760s | 10.200us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 45.480s | 10.160us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 58.150s | 10.140us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 42.540s | 10.160us | 0 | 1 | 0.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 39.630s | 10.220us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 22.951s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_sleep_frequency | 13.774s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_reset_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_reset_frequency | 11.113s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 993.500s | 943.577us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 126.420s | 118.468us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_all_reset_reqs | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 228.210s | 182.415us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_wdog_reset | 9.276s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 126.420s | 118.468us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 11.755s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 31.357s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 12.742s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 9.877s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_disabled | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 10.231s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 993.500s | 943.577us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sys_reset_info | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 347.390s | 310.099us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 428.660s | 412.064us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_req_reset | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 339.660s | 305.424us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_alert_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 369.660s | 331.199us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_rst | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 192.960s | 163.676us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 993.500s | 943.577us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_test | 13.239s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_escalations | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 23.470s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_all_escalation_resets | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 993.500s | 943.577us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_entropy | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_entropy | 19.205s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_crashdump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 369.660s | 331.199us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_ping_timeout | 1 | 1 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 262.380s | 267.859us | 1 | 1 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 71.173s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 85.474s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 87.016s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 73.670s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 69.828s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 23.470s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_jtag_access | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 9.261s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 10.503s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 9.261s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transitions | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 9.261s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_kmac_req | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 9.261s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_key_div | 1 | 1 | 100.00 | |||
| chip_sw_keymgr_dpe_key_derivation_prod | 423.510s | 351.362us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_broadcast | 1 | 10 | 10.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.910s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 9.950s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 9.627s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 9.639s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 9.261s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 453.400s | 359.333us | 1 | 1 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 192.370s | 157.192us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_execution_main | 12.599s | 0.000us | 0 | 1 | 0.00 | |
| chip_prim_tl_access | 80.610s | 117.992us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 96.970s | 129.400us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc | 1 | 2 | 50.00 | |||
| chip_sw_aes_enc | 215.010s | 173.124us | 1 | 1 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 40.960s | 10.200us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 1 | 2 | 50.00 | |||
| chip_sw_aes_enc | 215.010s | 173.124us | 1 | 1 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 40.960s | 10.200us | 0 | 1 | 0.00 | |
| chip_sw_aes_entropy | 1 | 1 | 100.00 | |||
| chip_sw_aes_entropy | 219.310s | 164.498us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 1 | 1 | 100.00 | |||
| chip_sw_aes_idle | 196.240s | 165.835us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc | 1 | 2 | 50.00 | |||
| chip_sw_hmac_enc | 215.240s | 173.736us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 43.910s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_hmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_hmac_enc_idle | 220.580s | 178.117us | 1 | 1 | 100.00 | |
| chip_sw_kmac_enc | 2 | 3 | 66.67 | |||
| chip_sw_kmac_mode_cshake | 211.520s | 167.249us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac | 255.000s | 188.825us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 44.140s | 10.400us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_keymgr | 1 | 1 | 100.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 453.400s | 359.333us | 1 | 1 | 100.00 | |
| chip_sw_kmac_app_lc | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 9.261s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_rom | 0 | 1 | 0.00 | |||
| chip_sw_kmac_app_rom | 16.829s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_entropy | 1 | 1 | 100.00 | |||
| chip_sw_kmac_entropy | 290.680s | 227.356us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_kmac_idle | 189.820s | 164.141us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_csrng | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 1573.550s | 2224.267us | 1 | 1 | 100.00 | |
| chip_sw_csrng_edn_cmd | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 1573.550s | 2224.267us | 1 | 1 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 0 | 1 | 0.00 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 9.757s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_known_answer_tests | 1 | 1 | 100.00 | |||
| chip_sw_csrng_kat_test | 240.210s | 175.900us | 1 | 1 | 100.00 | |
| chip_sw_edn_entropy_reqs | 1 | 1 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 1574.630s | 915.008us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 1 | 2 | 50.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 453.400s | 359.333us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 39.720s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_otbn_op | 1 | 2 | 50.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 3064.140s | 1501.653us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 40.130s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_otbn_rnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 310.800s | 245.046us | 1 | 1 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 310.800s | 245.046us | 1 | 1 | 100.00 | |
| chip_sw_otbn_idle | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 310.800s | 245.046us | 1 | 1 | 100.00 | |
| chip_sw_otbn_mem_scramble | 1 | 1 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 372.280s | 280.704us | 1 | 1 | 100.00 | |
| chip_sw_rom_access | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 192.370s | 157.192us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 192.370s | 157.192us | 0 | 1 | 0.00 | |
| chip_sw_sram_scrambled_access | 1 | 2 | 50.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 457.240s | 357.949us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.177s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_execution | 0 | 1 | 0.00 | |||
| chip_sw_sram_ctrl_execution_main | 12.599s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_lc_escalation | 0 | 2 | 0.00 | |||
| chip_sw_all_escalation_resets | 993.500s | 943.577us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity_escalation | 9.197s | 0.000us | 0 | 1 | 0.00 | |
| chip_otp_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 9.261s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_keys | 4 | 4 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 372.280s | 280.704us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 453.400s | 359.333us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 457.240s | 357.949us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 231.270s | 188.958us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 4 | 4 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 372.280s | 280.704us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 453.400s | 359.333us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 457.240s | 357.949us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 231.270s | 188.958us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_program | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 9.261s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_program_error | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_program_error | 11.346s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 10.503s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals | 0 | 6 | 0.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.910s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 9.950s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 9.627s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 9.639s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 9.261s | 0.000us | 0 | 1 | 0.00 | |
| chip_prim_tl_access | 80.610s | 117.992us | 0 | 1 | 0.00 | |
| chip_sw_otp_prim_tl_access | 0 | 1 | 0.00 | |||
| chip_prim_tl_access | 80.610s | 117.992us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_nvm_cnt | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_nvm_cnt | 9.959s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_sw_parts | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_sw_parts | 10.941s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_clk_outputs | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 22.951s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 1 | 7 | 14.29 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 40.130s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 40.960s | 10.200us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 43.910s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 39.720s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 44.140s | 10.400us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.177s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 215.630s | 161.169us | 1 | 1 | 100.00 | |
| chip_sw_soc_proxy_external_reset_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 186.650s | 156.224us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_irqs | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 186.650s | 156.224us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_wakeup_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_external_wakeup | 187.140s | 157.802us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_gpios | 1 | 1 | 100.00 | |||
| chip_sw_soc_proxy_gpios | 220.490s | 180.157us | 1 | 1 | 100.00 | |
| chip_sw_nmi_irq | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 401.960s | 269.313us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_rnd | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 246.250s | 183.269us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 217.420s | 179.980us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 231.270s | 188.958us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 428.660s | 412.064us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_double_fault | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 428.660s | 412.064us | 0 | 1 | 0.00 | |
| chip_sw_smoketest | 14 | 14 | 100.00 | |||
| chip_sw_aes_smoketest | 207.700s | 173.176us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_smoketest | 243.970s | 182.275us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_smoketest | 180.720s | 162.178us | 1 | 1 | 100.00 | |
| chip_sw_csrng_smoketest | 184.440s | 164.242us | 1 | 1 | 100.00 | |
| chip_sw_gpio_smoketest | 207.850s | 184.413us | 1 | 1 | 100.00 | |
| chip_sw_hmac_smoketest | 239.970s | 194.772us | 1 | 1 | 100.00 | |
| chip_sw_kmac_smoketest | 232.400s | 185.521us | 1 | 1 | 100.00 | |
| chip_sw_otbn_smoketest | 293.460s | 231.637us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_smoketest | 209.890s | 165.885us | 1 | 1 | 100.00 | |
| chip_sw_rv_plic_smoketest | 202.580s | 163.977us | 1 | 1 | 100.00 | |
| chip_sw_rv_timer_smoketest | 260.370s | 266.887us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_smoketest | 188.210s | 161.017us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 213.920s | 164.452us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest | 184.000s | 175.151us | 1 | 1 | 100.00 | |
| chip_sw_rom_functests | 0 | 1 | 0.00 | |||
| rom_keymgr_functest | 11.811s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_signed | 0 | 1 | 0.00 | |||
| chip_sw_uart_smoketest_signed | 14.739s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_boot | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 62.561s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_secure_boot | 0 | 1 | 0.00 | |||
| base_rom_e2e_smoke | 7.802s | 0.000us | 0 | 1 | 0.00 | |
| chip_lc_scrap | 0 | 4 | 0.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 199.510s | 167.624us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 164.470s | 171.352us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 172.710s | 172.664us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 157.530s | 172.056us | 0 | 1 | 0.00 | |
| chip_lc_test_locked | 0 | 2 | 0.00 | |||
| chip_sw_lc_walkthrough_testunlocks | 9.955s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 96.970s | 129.400us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough | 0 | 5 | 0.00 | |||
| chip_sw_lc_walkthrough_dev | 89.911s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 74.835s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 10.774s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_rma | 71.152s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 9.955s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 0 | 3 | 0.00 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 249.030s | 343.816us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 315.220s | 394.888us | 0 | 1 | 0.00 | |
| rom_volatile_raw_unlock | 17.631s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_raw_unlock | 0 | 1 | 0.00 | |||
| rom_raw_unlock | 17.553s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 0 | 1 | 0.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 51.763s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_inject_scramble_seed | 0 | 1 | 0.00 | |||
| chip_sw_inject_scramble_seed | 12.296s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 124.760s | 118.080us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 124.760s | 118.080us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 8.860s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 9.900s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 8.860s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 9.900s | 0.000us | 0 | 1 | 0.00 | |
| xbar_base_random_sequence | 1 | 1 | 100.00 | |||
| xbar_random | 47.420s | 43.743us | 1 | 1 | 100.00 | |
| xbar_random_delay | 6 | 6 | 100.00 | |||
| xbar_smoke_zero_delays | 10.020s | 12.705us | 1 | 1 | 100.00 | |
| xbar_smoke_large_delays | 266.540s | 2553.143us | 1 | 1 | 100.00 | |
| xbar_smoke_slow_rsp | 319.220s | 2037.395us | 1 | 1 | 100.00 | |
| xbar_random_zero_delays | 12.900s | 12.747us | 1 | 1 | 100.00 | |
| xbar_random_large_delays | 1022.720s | 9390.180us | 1 | 1 | 100.00 | |
| xbar_random_slow_rsp | 427.490s | 2685.878us | 1 | 1 | 100.00 | |
| xbar_unmapped_address | 2 | 2 | 100.00 | |||
| xbar_unmapped_addr | 78.960s | 42.558us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 51.910s | 38.826us | 1 | 1 | 100.00 | |
| xbar_error_cases | 2 | 2 | 100.00 | |||
| xbar_error_random | 133.400s | 370.105us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 51.910s | 38.826us | 1 | 1 | 100.00 | |
| xbar_all_access_same_device | 2 | 2 | 100.00 | |||
| xbar_access_same_device | 98.830s | 240.491us | 1 | 1 | 100.00 | |
| xbar_access_same_device_slow_rsp | 1914.010s | 12333.939us | 1 | 1 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 1 | 1 | 100.00 | |||
| xbar_same_source | 18.750s | 16.025us | 1 | 1 | 100.00 | |
| xbar_stress_all | 2 | 2 | 100.00 | |||
| xbar_stress_all | 673.090s | 1309.727us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_error | 335.540s | 282.378us | 1 | 1 | 100.00 | |
| xbar_stress_with_reset | 2 | 2 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 589.620s | 336.754us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_reset_error | 1780.380s | 1576.229us | 1 | 1 | 100.00 | |
| rom_e2e_smoke | 0 | 1 | 0.00 | |||
| rom_e2e_smoke | 10.675s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_output | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_output | 11.181s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_exception_c | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_exception_c | 25.594s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 37.469s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 11.036s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 8.887s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 8.087s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 9.999s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 105.038s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 8.860s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 8.810s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 11.680s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 8.232s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 110.361s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 13.592s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 16.601s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 15.143s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 10.592s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 155.677s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 25.593s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 22.544s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 18.476s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 21.154s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 104.469s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 25.220s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 10.278s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 12.826s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 27.161s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 21.310s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 14.890s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 23.232s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 17.967s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 14.854s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 5 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 57.502s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_dev | 9.119s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod | 14.599s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod_end | 15.090s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_rma | 11.865s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init | 0 | 3 | 0.00 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 11.377s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 15.393s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 33.896s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_static_critical | 0 | 1 | 0.00 | |||
| rom_e2e_static_critical | 11.043s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 1 | 1 | 100.00 | |||
| chip_sw_aes_masking_off | 246.880s | 187.854us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 157.460s | 134.069us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 12.210s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 24.029s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 12.968s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 18.532s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_alerts | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 993.500s | 943.577us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 11.598s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 222.140s | 176.988us | 0 | 1 | 0.00 | |
| chip_sw_coremark | 0 | 1 | 0.00 | |||
| chip_sw_coremark | 22.580s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_max_load | 0 | 1 | 0.00 | |||
| chip_sw_power_virus | 79.834s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 12.210s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 24.029s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 12.968s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 18.489s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 9.343s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 8.549s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 1 | 0.00 | |||
| rom_e2e_self_hash | 111.641s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 8 | 20 | 40.00 | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 48.650s | 10.260us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 286.650s | 203.519us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_kat_test | 202.920s | 163.574us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 180.550s | 161.142us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_0 | 470.420s | 327.563us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_10 | 417.750s | 300.498us | 1 | 1 | 100.00 | |
| chip_sw_dma_inline_hashing | 251.710s | 208.658us | 1 | 1 | 100.00 | |
| chip_sw_dma_abort | 275.960s | 210.526us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 18.650s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 15.961s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_otbn | 11.829s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_sw | 9.707s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_otbn | 8.268s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_sw | 9.780s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 9.269s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_sw | 10.369s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_otbn | 8.837s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_sw | 8.340s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_smoketest | 249.220s | 191.726us | 1 | 1 | 100.00 | |
| chip_sw_mbx_smoketest | 456.560s | 410.806us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 119 test runs | |||
| chip_sw_example_manufacturer | 55637633231256627243281613243622933739860448983942489835416442769221249097024 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.107s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_data_integrity_escalation | 105649089298473743934801940823766571897529425627904709297797928984869837467410 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.300s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sleep_pin_wake | 99622627666963015840355336684837699431894696726752368725270151307501762330913 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.651s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sleep_pin_retention | 55797669735378261947355214888958984381878826008460029322172870025863295521438 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.296s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx | 42872663069510094606237190558876415100219987631919503609273457357953478879099 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.296s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_bootstrap | 102661138178488772769637063942707190406288160943302238217770482601580380747306 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.689s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_inject_scramble_seed | 59542493648939486139267217789280671327471001275340818204426071168678349582486 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.854s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_exit_test_unlocked_bootstrap | 106306439608073826816683020843578495371486597173953825434573277116440151967711 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.674s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_rand_baudrate | 68858302394264663953448497092094609688480454046182785154390130901382912734091 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.232s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_alt_clk_freq | 108130478807181546493159338576791858914590804109901735644487400094704395896508 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.193s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_i2c_host_tx_rx | 105409865129627534327937857785733395619939843850315499039904990770809611695775 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.984s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_i2c_device_tx_rx | 16275650345188244739590073245954581682241054930987727474180919274910795647344 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.247s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_spi_device_tpm | 114533268485458964032860970832478512144710388977703366064112569802532213438772 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.525s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_spi_host_tx_rx | 61570983080972302848231214550271237726707212113630820470634711033070866377440 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.791s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_otp_hw_cfg | 106513204037163523769026674288363618028669063136814081497710438680129687084207 | None |
---- STDERR ----
Another command (pid=1179879) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=1180546) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 112538401118086709801739428154885879230082935205778510770053901316911979353202 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.711s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_dev | 11816080534704061562393013318266670256288398120298354726277823037840183653937 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.321s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_prod | 54871292912321727718639708894459649554496372244717205376120761510486619619585 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.263s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 1112760808863461614954562666703781680785885186222849529602183716083971553308 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.282s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_vendor_test_csr_access | 27338758790539879917299073219101202757515173429464114520094831610215748783185 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.479s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_nvm_cnt | 63636208035119826663404088648255230466199206853812475894596135739557975709336 | None |
---- STDERR ----
Another command (pid=468895) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_sw_parts | 105706181835937265844271857685952037827925966647101072934193764230193977408022 | None |
Another command (pid=476786) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=462379) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=480101) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_transition | 78451927263486127113467416790319170781411517254501686231234423276492401163847 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.324s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_dev | 16523297165292644524117385464037839645091418046884044458741775112747406542940 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.533s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prod | 30700960397078828997122440318051550429028345095840762627549298456858687149744 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.790s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prodend | 85767447218739344579633540761446523182858658142866691080042032977294891698173 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.246s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_rma | 80106899305436337455576507739565971562428578789026595665195665896259918559830 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.603s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_testunlocks | 81619746429034134973064451695642029595046473011528947474050850909687554262389 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.292s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_main_power_glitch_reset | 34367179011131830286484682182784424710398175706475970581459397654334745925662 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.314s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 81994773881957787406801909485991153707047407632443832453453003656141694549686 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.250s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 82707341978717253156459805940402802654904500573582520434406700236604151125735 | None |
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.139s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 108072505242501962315018826846825755631246602563225225806044791511924705612158 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.699s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_disabled | 23471612224509195291372835918646526944337982799146446672470653041123740472916 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.321s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_wdog_reset | 2319206714183170418797867156041115371327309378238355418380960508189411817529 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.264s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_test | 81277154567587084754486614085118663342676383820503331308519456859700137255439 | None |
Another command (pid=671167) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_escalation | 98565845764698250623630137635699037092620520192847018889007941924549201062269 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.713s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 96306159531048258918902725473585430953423060568145674214888754086675193238431 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.205s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 108208559139390613693185837243352027609622987396133373477058469625648956808422 | None |
Another command (pid=460397) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=375768) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=463338) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_pings | 61225576442304255930675141597483319343917014580211332968617246028722807503693 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.179s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_clkoff | 98987615456056061467374407608445622262549879798348738176029771760295807200096 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.725s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_reset_toggle | 17595025015977719611837495572277342519944932610569185555164301070122848690289 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 5.188s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_entropy | 47406631296069938214545401492316155473597632387252451992819831254159673564044 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.208s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 17647048355187073835560681315986016886712277018981208372787417733158945283130 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.282s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_kmac_app_rom | 104181390118694575956145289425959747768970824637471073219555872655820905135030 | None |
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery labels(data, //sw/device/tests:kmac_app_rom_test_sim_dv) union labels(srcs, //sw/device/tests:kmac_app_rom_test_sim_dv) --ui_event_filters=-info --noshow_progress --//hw/top=darjeeling --//hw/top=darjeeling --output=starlark
---- STDOUT ----
---- STDERR ----
Another command (pid=1152139) is running. Waiting for it to complete on the server (server_pid=207063)...
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11708405134166913652664206533644094325414525492549878537611561730843019119238 | None |
---- STDERR ----
Another command (pid=1360038) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=1360189) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_execution_main | 93044418760207514690671004207836151207872003157638010330044738049311257799538 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.741s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_coremark | 114846115991831241616193457604322566212999162704046450455946942352161908730672 | None |
Another command (pid=460949) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_clkmgr_reset_frequency | 75727048203002612342014040769613117468226498296187132618530301074008391522717 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_reset_frequency_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.717s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_clkmgr_sleep_frequency | 33222591566380857548064092557061067902270918011572631118051042740165335991068 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.412s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_ast_clk_outputs | 83653298179067906670307560777027008252405765962612920752298159562527807732597 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:ast_clk_outs_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.617s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_program_error | 10469521792503515325451489633134722078192647459762115314252010714332268929814 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.955s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 98234209549279360430942302330757356496387982552794758711047338519687871655953 | None |
---- STDERR ----
Another command (pid=1309385) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_wakeup | 17083316103127588169478842255549654881715717603232180642168859982157838918347 | None |
Another command (pid=1307276) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=1303734) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=1304439) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_escalation_reset | 37694354868527989798702137243606288640750184905511467946378853024874474353030 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.302s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_power_virus | 80438564442769514255120516994437118768559203643816134352334946857157456780840 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:power_virus_systemtest_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.214s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| base_rom_e2e_smoke | 46646835242559398240779411203672616380298879045031867432512815476133227181396 | None |
_deploy_software_collateral(args)
~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
^^^^^^^^^^^^^^^^^^^
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_smoke | 14603349039812045790398119422362638972381334078053335111172863389190636270527 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_shutdown_exception_c | 73184923947111951070226491082046148492384441866228762737521036168391379076002 | None |
Another command (pid=533263) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=569432) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=577807) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_shutdown_output | 72559188430840607291903157628652796193916671141708868117378787476585879430754 | None |
---- STDERR ----
Another command (pid=533911) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=546258) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 61097909341511632080635814832757284175253690584569179152454812622811756186947 | None |
Another command (pid=336248) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=338937) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=354890) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 103813685725441008470006374944854953753305646891345231601380487870966054550262 | None |
Another command (pid=465453) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=514817) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=518850) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 18036044362878553222602658541671740252911532346995190190364293018869792282661 | None |
---- STDERR ----
Another command (pid=460949) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 19024281233736903607982515125581452612249400303796330285195225009611811089525 | None |
---- STDERR ----
Another command (pid=518850) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 55148690124781649561993835216281539104465554897516968993444361021257413820922 | None |
Another command (pid=517798) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=520868) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=526080) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 79906035396351199775503524481083887057955151936909134151373319659146238974390 | None |
Another command (pid=356124) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=370381) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=318138) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 5642883024204672893832215398457809173101998293011187729410340653252274451860 | None |
---- STDERR ----
Another command (pid=482286) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 99487754494201842074177759442158468706410343551558485995732533398269521372835 | None |
---- STDERR ----
Another command (pid=496932) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=502562) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 4524650204152968505162817435814105923220895217877676520642241912047957931538 | None |
Another command (pid=460949) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=512832) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=501143) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 11005026787696723527097914466068223226331752558435349353328777295768897665914 | None |
---- STDERR ----
Another command (pid=501645) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 55735980372227022763004200394670344298655896049510374379954105070403732500776 | None |
Another command (pid=355917) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=356124) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=370381) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 13790160437649840430092920623555004309313019702682895315003236581769993365736 | None |
---- STDERR ----
Another command (pid=465453) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 91028480487491638313936903225527531128336583895074799672847257256995816374532 | None |
---- STDERR ----
Another command (pid=510113) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=517798) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 48736039021971253348441249210155236834056270452221325907280482995461646004262 | None |
Another command (pid=514817) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=518850) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=511873) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 43310257238515866258072993736124421437984674120087511095056830794118267802262 | None |
Another command (pid=487548) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=497312) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=501645) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 24044133198893396965945429153199047196706977709520806781282424144094379322146 | None |
Another command (pid=520412) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=501090) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=517798) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 105827513355806834905660277651647029825658302749603885146095676964418485476946 | None |
Another command (pid=584605) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=533489) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=582924) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 50345885322747460731323139822096054658256805116106902557967676257580138096660 | None |
---- STDERR ----
Another command (pid=568160) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 66081732377551815713789129966636138609149297163052681527545822070348588255311 | None |
Another command (pid=564791) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=565962) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=567220) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 91549699757535747865198746234613181094783804258975430571332906635640873537 | None |
Another command (pid=583500) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=584605) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=578055) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 93891408596784945658350062674285206044427384017494604924568021927104869453979 | None |
Another command (pid=453444) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=456292) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=392283) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 72639293076640910819936402751614576114236954207971029783213219251035507061681 | None |
Another command (pid=586653) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=591695) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=598397) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 23763494055171336429206776989632036600650557993720732634787792828703970168727 | None |
---- STDERR ----
Another command (pid=563759) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 27263203849984734028968247050938248289555800101468205372354514014730121056636 | None |
Another command (pid=546532) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=570103) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=576793) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 76353949013198389674323989376483106114842567532545666145107971689996514670308 | None |
---- STDERR ----
Another command (pid=622805) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 10155123651576794317929355867452463291713167661139584981496107194595876979847 | None |
---- STDERR ----
Another command (pid=338937) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 57234834345369938187484847580460483951535703420154904790340399059991754783291 | None |
Another command (pid=577807) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=582515) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=533489) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 32306183839942670250093466611186383760118958789979067711881791508724950933908 | None |
Another command (pid=552260) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=615315) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=568346) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 49605399122124373783305619414040371023500696339717194698999916564056178322690 | None |
---- STDERR ----
Another command (pid=620888) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=607226) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 91572640768480774429041004185480262225222913543681301705784414542035896167045 | None |
---- STDERR ----
Another command (pid=606455) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=612170) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 58274956293326757726405623214096446944058096535708255699599970538228139007198 | None |
---- STDERR ----
Another command (pid=285168) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 17328017283127530474285377333611680598526045505981592940170143254357131228701 | None |
---- STDERR ----
Another command (pid=462379) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=480101) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 112677115776445731812760270543430031692582094457666061392780638961126358623263 | None |
Another command (pid=499101) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=482286) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=496932) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 92301078974201974082980556021928435790779392498761769836588340255968931299874 | None |
Another command (pid=496932) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=497726) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=501645) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 102996258458302796184722473827449673739258061401223892340935454583210732470027 | None |
Another command (pid=487548) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=497312) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=501645) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_test_unlocked0 | 44975984466071834440444448118008382081159018999911139761879887854106584155128 | None |
Another command (pid=532964) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=534459) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=533911) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_dev | 6500333030520761858408917450500228379750715610962247470254002772001393218962 | None |
Another command (pid=568223) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=570511) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=572231) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_rma | 93155688498480021289124429311023736277739472976008775378958291114242843112513 | None |
Another command (pid=538987) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=533911) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=541640) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 25336474052364736990472362178414227877806328101903636097115377493173217918053 | None |
Another command (pid=469205) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=355005) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=467750) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_dev | 8513570427113669629445951167768749929532911037701376606704309975532133134641 | None |
Another command (pid=370381) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=318138) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=361170) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_rma | 7713948736883540276835305939748484482962615242762094436764452692736335276302 | None |
---- STDERR ----
Another command (pid=318138) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=314111) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_static_critical | 70638112546989465854225451558884015851352762397502400943563356708070027973157 | None |
---- STDERR ----
Another command (pid=568346) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_meas | 24021391303619109022972848787109011387452982715935804982768662009984283774324 | None |
---- STDERR ----
Another command (pid=533911) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_no_meas | 33798688415418691792497173590271389960921665645526540489181741549932670098645 | None |
Another command (pid=532595) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=541244) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=540182) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 38067273594046803259772888976293959566569528539338134739264159348577526716926 | None |
Another command (pid=591695) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=598397) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=575646) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 6260925306184399657855188429783621821391493408743681159179426205899606315623 | None |
Another command (pid=285168) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=339944) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=336248) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 90706821157097293503301352677424675723046220628940950883881182656128079165675 | None |
---- STDERR ----
Another command (pid=285168) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_otbn | 77840348230763728242033968111406746270800237779299214902651186963693309775687 | None |
Another command (pid=603912) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=539163) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=598053) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_sw | 85200734579304529155786224157893335460728585858693656019638016652630304407548 | None |
Another command (pid=598397) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=595793) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=539163) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_otbn | 105992190968573268938627326749648411669380498085928636257587962256481960837695 | None |
---- STDERR ----
Another command (pid=598053) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_sw | 109649077568118460213030285193827209936382810908400165091044906295502434984770 | None |
Another command (pid=605496) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=599030) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=606935) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 100693568906394369100341817341328103783478076016464811931536534037274436756464 | None |
Another command (pid=598397) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=595793) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=539163) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_sw | 73427121445162874589666425924004346916960598628126215067809002572091214596308 | None |
Another command (pid=598053) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=609445) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=599030) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_otbn | 42555280421030808447498682348690664271942065959352038242486823724729195314170 | None |
---- STDERR ----
Another command (pid=606935) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_sw | 78132558180216012477822474893282559244514956396984208558656477753379630515787 | None |
---- STDERR ----
Another command (pid=606935) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 22276875624957019405207482684058812086506593150634817740493011053484303095401 | None |
Another command (pid=336248) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=338937) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=354890) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 40405716591062530800546344251725743761676382161696739892871019120425944682118 | None |
Another command (pid=339944) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=336248) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=351014) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 102872359374865356511229295666576822920760803253473387912126712786661405513152 | None |
Another command (pid=461560) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=459158) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=468895) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_smoketest_signed | 111235169239335714512788156558283176947213907005209428252994983463625504711872 | None |
Another command (pid=491262) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=483540) is running. Waiting for it to complete on the server (server_pid=207063)...
Another command (pid=494171) is running. Waiting for it to complete on the server (server_pid=207063)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_keymgr_functest | 61382785222317654794473373405992415892241157127242210883225100108356195036989 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.227s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| UVM_FATAL @ * us: (dv_utils_pkg.sv:253) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" | 12 test runs | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 102296700197670623479566589517656002142620374064660697449134667731430891027739 | 312 |
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aes_enc_jitter_en | 54242564768666397948993675035551403654413800630227163324055954920732411913667 | 312 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_enc_jitter_en | 78777574293787069138336502591624399681758188298917713367778862867519401249224 | 312 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 112305846681235108883386569796305754058568460162091087416156545362608676153216 | 312 |
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_kmac_mode_kmac_jitter_en | 95123199621722539592402632865316745791169857047402346120297602642338123234370 | 312 |
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 88915677374937901509055343718282659008373491424460294662371411459770371589432 | 312 |
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aes_enc_jitter_en_reduced_freq | 61347166583130512050351923050018313329674095900363990396959239874292348931015 | 312 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_enc_jitter_en_reduced_freq | 14572111971408723860597025856171086273043096758816869921915721561513832161970 | 312 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 9154902272936101814881600232414516081417365748094991968689610755935545483516 | 312 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 111102007911444141600433144448526810750437761200078910193168573340623382139992 | 312 |
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 89608996797981795420470130645709024238980512108376701643853421541379643427374 | 312 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_edn_concurrency_reduced_freq | 109777559414554195966128992596172547046405540881111215790305694798217137088100 | 312 |
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((~rst_ni) === (~seed_en_q))' | 10 test runs | |||
| chip_sw_lc_ctrl_rma_to_scrap | 8864987515952056972054046584977165441017246973069815231968081849165093887288 | 333 |
UVM_ERROR @ 167.624000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 167.624000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_raw_to_scrap | 49602377454564056444328849086274105812106046061935155938943700121681193913832 | 322 |
UVM_ERROR @ 171.352000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 171.352000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_test_locked0_to_scrap | 8000008121898899910797790488074939199659462651516445175442979282615043681992 | 322 |
UVM_ERROR @ 172.664000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 172.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_rand_to_scrap | 110578951460211107265937010829000158938064660710610583970442860073205228123046 | 322 |
UVM_ERROR @ 172.056000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 172.056000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_volatile_raw_unlock | 29282970376332565723878850062601103371705292299818157148034500061516970212905 | 325 |
UVM_ERROR @ 343.816000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 343.816000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 16579190944001664585154036294342745748015641080446694950425934628532829673386 | 328 |
UVM_ERROR @ 394.888000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 394.888000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 96495257211643747422515075932932439000539793451140605845568834090888147731828 | 315 |
UVM_ERROR @ 118.468000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 118.468000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rom_ctrl_integrity_check | 46069960390882600033509615500179206694030390000746692241419931344621817246348 | 324 |
UVM_ERROR @ 157.192000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 157.192000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_prim_tl_access | 58078652298082403515461069494682274548549670743177287376899107864247898062940 | 234 |
UVM_ERROR @ 117.992000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 117.992000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 50005423610009843960350189812847677209731933071843241845745237262351261329589 | 212 |
UVM_ERROR @ 129.400000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 129.400000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((!rstreqs[*]) && (reset_cause != HwReq))' | 5 test runs | |||
| chip_sw_rstmgr_cpu_info | 105386791966462042481890700703002990724126799681303575140970873674986455001922 | 346 |
UVM_ERROR @ 412.064000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 412.064000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_aes_trans | 65947912015313770821522566428325103353663808818349522670907684650154043413478 | 323 |
UVM_ERROR @ 185.280000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_hmac_trans | 56598002383984066321965301205487503511422490325528759126778784921868096903340 | 323 |
UVM_ERROR @ 185.200000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.200000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_kmac_trans | 80954028542315477168380920583541358882247112164774944268483657289638244380684 | 323 |
UVM_ERROR @ 185.312000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.312000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_otbn_trans | 33203730012000032221771807136039798986266674850251331598447764669041688429950 | 323 |
UVM_ERROR @ 185.280000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode | 3 test runs | |||
| chip_csr_bit_bash | 79811941682890544110524288545947021849609335370237397183859310425218922114671 | 136 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_aliasing | 113830115834062116655572929702410691271630214629371941613701532617727593475561 | 136 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_same_csr_outstanding | 90570241083755938011670692468772839774461565204478025969144155207477152379245 | 136 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (jtag_riscv_driver.sv:221) [jtag_riscv_agent_pkg] Check failed sbcs_val[SbAccess32] == * (* [*] vs * [*]) expect SBA width to be * bits! | 2 test runs | |||
| chip_jtag_csr_rw | 110279111173209960803801174707517131046520425694116821076127056402575818427465 | 5956 |
UVM_INFO @ 132.603000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_jtag_mem_access | 35053686670395903627633215596610390078585796771721181860610448250758898282679 | 5956 |
UVM_INFO @ 132.270000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode | 1 test run | |||
| chip_sw_example_rom | 34259424487592790448636813248080009507877326342868879428877603388811430684131 | 284 |
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size | 1 test run | |||
| chip_sw_all_escalation_resets | 46069021177316030849649068681946710940079973381081905905475472660056460604886 | 350 |
UVM_INFO @ 943.577000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path | 1 test run | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 98226459138568085330878135458339562303516299034815857987264286109733791065094 | 313 |
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | 1 test run | |||
| chip_sw_spi_device_pass_through_collision | 93525555507419256607055296008788343215539858355514705278511572776589092127956 | 334 |
UVM_INFO @ 273.729000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | 1 test run | |||
| chip_sw_otp_ctrl_escalation | 14496447242805444418815997030143933145391011916831680156498978638584354119575 | 328 |
UVM_ERROR @ 176.988000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.988000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size | 1 test run | |||
| chip_sw_rstmgr_alert_info | 89447606761013594710211150381115028819264302420368217394843485095060039104161 | 342 |
UVM_INFO @ 331.199000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! | 1 test run | |||
| chip_sw_soc_proxy_smoketest | 28492739109810585734724792510088088357783609080069221647515788638826143262772 | 321 |
UVM_INFO @ 156.224000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * | 1 test run | |||
| chip_sw_soc_proxy_external_wakeup | 102417360429401519947459970253091042836365517514095738877626603328468015478981 | 319 |
UVM_INFO @ 157.802000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec | 1 test run | |||
| chip_sw_aon_timer_irq | 56909488450807745319772279424936795496434568257319702175770204029794773108129 | 320 |
UVM_INFO @ 549.306000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds | 1 test run | |||
| chip_sw_aon_timer_wdog_bite_reset | 68806840787932534015375349394128901042559538443044848770910299910539191590705 | 321 |
UVM_INFO @ 182.415000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired | 1 test run | |||
| chip_sw_rv_core_ibex_nmi_irq | 20264521747835793896795720444929270607340085984067977374365788372128053979126 | 322 |
UVM_INFO @ 269.313000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). | 1 test run | |||
| chip_tl_errors | 39005914177584971154175109729608235790184387474736191560425370476517765749961 | 231 |
TL item was: req: (cip_tl_seq_item@31714) { a_addr: 'h40560 a_data: 'h912a591d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1859a d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 118.080000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Error-[CNST-CIF] Constraints inconsistency failure | 1 test run | |||
| chip_padctrl_attributes | 15787065000781697955047691576373886861447074771451045146091905559297218769583 | 281 |
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
|
| UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== | 1 test run | |||
| chip_sw_dma_abort | 29363125383091815573627080599567493391246429799271684837336449580994797516920 | 340 |
UVM_INFO @ 210.526000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|