Simulation Results: clkmgr

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.22 %
  • code
  • 68.19 %
  • assert
  • 88.84 %
  • func
  • 59.62 %
  • line
  • 81.56 %
  • branch
  • 86.53 %
  • cond
  • 76.53 %
  • toggle
  • 96.32 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.410s 78.722us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.820s 25.963us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.720s 13.825us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 3.550s 348.668us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.830s 12.582us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.000s 20.160us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.720s 13.825us 1 1 100.00
clkmgr_csr_aliasing 0.830s 12.582us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.620s 110.936us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.180s 50.307us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.830s 16.268us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.410s 78.722us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.720s 7.216us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.690s 3.184us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.720s 7.216us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.800s 110.575us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.020s 45.348us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.100s 23.584us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.100s 23.584us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.820s 25.963us 1 1 100.00
clkmgr_csr_rw 0.720s 13.825us 1 1 100.00
clkmgr_csr_aliasing 0.830s 12.582us 0 1 0.00
clkmgr_same_csr_outstanding 0.960s 26.799us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.820s 25.963us 1 1 100.00
clkmgr_csr_rw 0.720s 13.825us 1 1 100.00
clkmgr_csr_aliasing 0.830s 12.582us 0 1 0.00
clkmgr_same_csr_outstanding 0.960s 26.799us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.260s 52.784us 0 1 0.00
clkmgr_tl_intg_err 0.850s 10.950us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 67.451us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 67.451us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 67.451us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 67.451us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.990s 12.688us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.850s 10.950us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.720s 7.216us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.690s 3.184us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 67.451us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.330s 54.202us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.720s 13.825us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.260s 52.784us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.720s 13.825us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.720s 13.825us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.260s 52.784us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.720s 6.043us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.020s 130.141us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 81495154941679049125067869298675247440530298936786557803381866198696853369695 78
UVM_INFO @ 3183523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 75373640281410664773233998729515445452745958687097408095156727158342145270919 79
UVM_INFO @ 130140940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 41034846440764607253851035191911933799312109989080812844206348423791085864433 122
UVM_INFO @ 110575125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 32767720703821988402568606138684974727820668978982528802589768756302995438871 75
UVM_INFO @ 12688055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 105225170939048744969058974125351230627486956109958819824561214024721032903767 85
UVM_INFO @ 10950026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 2333133265191287914573327465783945461791701009801796235298971090948125860549 75
UVM_INFO @ 12581847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 107012932768817987501821625390927818339154370132579406270711339569423511426121 75
UVM_INFO @ 7216172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 5763907028860268068865399329799733062910161458958500631790220194077453866686 74
UVM_INFO @ 6043359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 3167055384635996575630842912700720453411666399963910650221357323583201372984 131
UVM_INFO @ 52784006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 8374382413760134645142023549683598089712281425816600929395311645965996547078 75
UVM_INFO @ 348667696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 88722028473389997932575148242069156945176605620688878812637065814563908658753 76
UVM_INFO @ 26798952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_csr_mem_rw_with_rand_reset 111058736738682206730058095538094113958401062111118260951077050980891358519995 76
UVM_INFO @ 20160453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---