Simulation Results: csrng

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.44 %
  • code
  • 92.48 %
  • assert
  • 94.76 %
  • func
  • 78.08 %
  • block
  • 97.16 %
  • line
  • 97.84 %
  • branch
  • 92.94 %
  • toggle
  • 93.44 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 48.714us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 30.740us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 25.491us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 74.000s 7921.198us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 45.235us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 195.201us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 25.491us 1 1 100.00
csrng_csr_aliasing 2.000s 45.235us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
alerts 1 1 100.00
csrng_alert 10.000s 631.100us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 4.000s 275.511us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 4.000s 275.511us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 175.000s 4750.443us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 17.332us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 59.749us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 8.000s 461.060us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 8.000s 461.060us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 30.740us 1 1 100.00
csrng_csr_rw 1.000s 25.491us 1 1 100.00
csrng_csr_aliasing 2.000s 45.235us 1 1 100.00
csrng_same_csr_outstanding 3.000s 120.490us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 30.740us 1 1 100.00
csrng_csr_rw 1.000s 25.491us 1 1 100.00
csrng_csr_aliasing 2.000s 45.235us 1 1 100.00
csrng_same_csr_outstanding 3.000s 120.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 44.176us 1 1 100.00
csrng_tl_intg_err 7.000s 412.614us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 18.814us 0 1 0.00
csrng_csr_rw 1.000s 25.491us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 10.000s 631.100us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 175.000s 4750.443us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
csrng_sec_cm 2.000s 44.176us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
csrng_sec_cm 2.000s 44.176us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
csrng_sec_cm 2.000s 44.176us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
csrng_sec_cm 2.000s 44.176us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
csrng_sec_cm 2.000s 44.176us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 10.000s 631.100us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 175.000s 4750.443us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 10.000s 631.100us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 7.000s 412.614us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
csrng_sec_cm 2.000s 44.176us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
csrng_sec_cm 2.000s 44.176us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 6.000s 436.051us 1 1 100.00
csrng_err 2.000s 34.963us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 29010869852167946314976832108985225596423336977804747948927913916722532979391 100
UVM_INFO @ 275511390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 8051482627235759312640291779612377106211173079084968679587548176439239450568 99
UVM_INFO @ 18813830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 56863728064365660110997577690624441848809704971360319975336050101366569947173 None