Simulation Results: dma

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.72 %
  • code
  • 90.38 %
  • assert
  • 96.50 %
  • func
  • 61.27 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1004.268us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 1359.181us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 503.795us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 17.067us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 63.004us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 912.959us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 268.011us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 221.268us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 63.004us 1 1 100.00
dma_csr_aliasing 3.000s 268.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 20.000s 7497.357us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 106.000s 33608.699us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 143.000s 23741.612us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 143.000s 23741.612us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 106.000s 33608.699us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 1328.000s 288048.756us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 143.000s 23741.612us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 3.000s 1131.508us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 65.000s 14110.652us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 14.191us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 15.569us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 186.025us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 186.025us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 17.067us 1 1 100.00
dma_csr_rw 1.000s 63.004us 1 1 100.00
dma_csr_aliasing 3.000s 268.011us 1 1 100.00
dma_same_csr_outstanding 2.000s 63.723us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 17.067us 1 1 100.00
dma_csr_rw 1.000s 63.004us 1 1 100.00
dma_csr_aliasing 3.000s 268.011us 1 1 100.00
dma_same_csr_outstanding 2.000s 63.723us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 15.000s 689.048us 1 1 100.00
dma_generic_stress 1328.000s 288048.756us 1 1 100.00
dma_handshake_stress 143.000s 23741.612us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 477.209us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 153.684us 1 1 100.00
dma_sec_cm 1.000s 17.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 124.000s 30776.956us 1 1 100.00
dma_longer_transfer 3.000s 103.233us 1 1 100.00
dma_stress_all_with_rand_reset 6.000s 1339.134us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 73619862527274266263347704066220461285644470256343314504983065596069914975062 95
UVM_INFO @ 1339133884ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---