Simulation Results: edn/edn0

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.28 %
  • code
  • 81.26 %
  • assert
  • 95.35 %
  • func
  • 49.23 %
  • block
  • 93.51 %
  • line
  • 96.59 %
  • branch
  • 86.07 %
  • toggle
  • 65.64 %
  • FSM
  • 76.74 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 42.709us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 39.811us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 28.584us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 337.600us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 66.548us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 27.294us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 28.584us 1 1 100.00
edn_csr_aliasing 2.000s 66.548us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 81.020us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 81.020us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 81.020us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 30.863us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 98.708us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 45.692us 1 1 100.00
disable 1 2 50.00
edn_disable 1.000s 33.601us 1 1 100.00
edn_disable_auto_req_mode 4.000s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.000s 321.891us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 56.659us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 18.556us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 55.490us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 55.490us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 39.811us 1 1 100.00
edn_csr_rw 1.000s 28.584us 1 1 100.00
edn_csr_aliasing 2.000s 66.548us 1 1 100.00
edn_same_csr_outstanding 2.000s 36.317us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 39.811us 1 1 100.00
edn_csr_rw 1.000s 28.584us 1 1 100.00
edn_csr_aliasing 2.000s 66.548us 1 1 100.00
edn_same_csr_outstanding 2.000s 36.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 2088.462us 1 1 100.00
edn_tl_intg_err 1.000s 71.696us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 48.221us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 98.708us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 2088.462us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 2088.462us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 2088.462us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 2088.462us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 98.708us 1 1 100.00
edn_sec_cm 7.000s 2088.462us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 98.708us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.000s 71.696us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 14.000s 2103.022us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 18365786324778884886285476194947235680033636374047995437522713866935638307325 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---