Simulation Results: edn/edn1

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.91 %
  • code
  • 81.18 %
  • assert
  • 97.14 %
  • func
  • 79.41 %
  • line
  • 98.10 %
  • branch
  • 92.86 %
  • cond
  • 89.31 %
  • toggle
  • 85.88 %
  • FSM
  • 39.77 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.740s 53.064us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.780s 164.187us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 19.864us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.790s 322.246us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 26.107us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.430s 30.874us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 19.864us 1 1 100.00
edn_csr_aliasing 1.030s 26.107us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.870s 147.287us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.870s 147.287us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.870s 147.287us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 25.340us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.900s 121.377us 1 1 100.00
errs 1 1 100.00
edn_err 0.880s 39.017us 1 1 100.00
disable 1 2 50.00
edn_disable 0.770s 47.494us 1 1 100.00
edn_disable_auto_req_mode 1.300s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.470s 299.416us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 14.389us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.790s 19.856us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.320s 94.403us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.320s 94.403us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.780s 164.187us 1 1 100.00
edn_csr_rw 0.810s 19.864us 1 1 100.00
edn_csr_aliasing 1.030s 26.107us 1 1 100.00
edn_same_csr_outstanding 0.860s 12.761us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.780s 164.187us 1 1 100.00
edn_csr_rw 0.810s 19.864us 1 1 100.00
edn_csr_aliasing 1.030s 26.107us 1 1 100.00
edn_same_csr_outstanding 0.860s 12.761us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.530s 1080.804us 1 1 100.00
edn_tl_intg_err 1.810s 443.715us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 17.330us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.900s 121.377us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.530s 1080.804us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.530s 1080.804us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.530s 1080.804us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.530s 1080.804us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.900s 121.377us 1 1 100.00
edn_sec_cm 3.530s 1080.804us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.900s 121.377us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.810s 443.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 87.790s 56816.501us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 103828933117491032154398700279239484362599616308508665767388359210131472913505 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---