Simulation Results: hmac

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.91 %
  • code
  • 96.00 %
  • assert
  • 96.74 %
  • func
  • 28.99 %
  • block
  • 97.51 %
  • line
  • 98.44 %
  • branch
  • 93.76 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 15.000s 11980.726us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 76.753us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 19.737us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 2288.649us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 342.430us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.000s 94.385us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 19.737us 1 1 100.00
hmac_csr_aliasing 5.000s 342.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 68.000s 120941.564us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 56.000s 1557.069us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 2522.566us 1 1 100.00
hmac_test_sha384_vectors 465.000s 39096.355us 1 1 100.00
hmac_test_sha512_vectors 403.000s 15988.958us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 411.158us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 470.810us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 1196.112us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.000s 1379.980us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 250.000s 8301.076us 1 1 100.00
error 1 1 100.00
hmac_error 49.000s 18367.136us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 36.000s 3141.560us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 15.000s 11980.726us 1 1 100.00
hmac_long_msg 68.000s 120941.564us 1 1 100.00
hmac_back_pressure 56.000s 1557.069us 1 1 100.00
hmac_datapath_stress 250.000s 8301.076us 1 1 100.00
hmac_burst_wr 15.000s 1379.980us 1 1 100.00
hmac_stress_all 115.000s 44322.272us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 15.000s 11980.726us 1 1 100.00
hmac_long_msg 68.000s 120941.564us 1 1 100.00
hmac_back_pressure 56.000s 1557.069us 1 1 100.00
hmac_datapath_stress 250.000s 8301.076us 1 1 100.00
hmac_wipe_secret 36.000s 3141.560us 1 1 100.00
hmac_test_sha256_vectors 10.000s 2522.566us 1 1 100.00
hmac_test_sha384_vectors 465.000s 39096.355us 1 1 100.00
hmac_test_sha512_vectors 403.000s 15988.958us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 411.158us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 470.810us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 1196.112us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 15.000s 11980.726us 1 1 100.00
hmac_long_msg 68.000s 120941.564us 1 1 100.00
hmac_back_pressure 56.000s 1557.069us 1 1 100.00
hmac_datapath_stress 250.000s 8301.076us 1 1 100.00
hmac_burst_wr 15.000s 1379.980us 1 1 100.00
hmac_error 49.000s 18367.136us 1 1 100.00
hmac_wipe_secret 36.000s 3141.560us 1 1 100.00
hmac_test_sha256_vectors 10.000s 2522.566us 1 1 100.00
hmac_test_sha384_vectors 465.000s 39096.355us 1 1 100.00
hmac_test_sha512_vectors 403.000s 15988.958us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 411.158us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 470.810us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 1196.112us 1 1 100.00
hmac_stress_all 115.000s 44322.272us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 115.000s 44322.272us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 29.328us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 17.301us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 274.089us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 274.089us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 76.753us 1 1 100.00
hmac_csr_rw 1.000s 19.737us 1 1 100.00
hmac_csr_aliasing 5.000s 342.430us 1 1 100.00
hmac_same_csr_outstanding 1.000s 42.786us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 76.753us 1 1 100.00
hmac_csr_rw 1.000s 19.737us 1 1 100.00
hmac_csr_aliasing 5.000s 342.430us 1 1 100.00
hmac_same_csr_outstanding 1.000s 42.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 388.297us 1 1 100.00
hmac_tl_intg_err 4.000s 1137.683us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 1137.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 15.000s 11980.726us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.000s 48.642us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 14.000s 592.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 5.000s 240.641us 1 1 100.00