Simulation Results

Simulation Results: i2c

03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.69 %

code
86.36 %

assert
97.46 %

func
79.24 %

block
96.22 %

line
95.68 %

branch
93.24 %

toggle
72.35 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		82.93%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	113.000s	1234.718us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	16.000s	2784.213us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	34.556us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	80.411us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.000s	296.835us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	26.248us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	101.804us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	80.411us	1	1	100.00
	i2c_csr_aliasing	2.000s	26.248us	1	1	100.00

34/41 passed

82.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	115.249us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	127.000s	48812.804us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	3084.000s	7505.573us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	32.739us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1388.000s	2286.445us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	134.565us	1	1	100.00
	i2c_host_fifo_fmt_empty	14.000s	1292.214us	1	1	100.00
	i2c_host_fifo_reset_rx	5.000s	283.100us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	2209.000s	6813.714us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	19.000s	693.976us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	5.192us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	421.941us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	32.000s	97313.935us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	802.998us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	17.000s	1390.240us	1	1	100.00
	i2c_target_intr_smoke	6.000s	3763.821us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	318.234us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	161.754us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3601.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	17.000s	1390.240us	1	1	100.00
	i2c_target_intr_stress_wr	3600.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.000s	5351.520us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	257.000s	4987.789us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	1198.701us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	4.000s	280.844us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	333.065us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	1480.337us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	3084.000s	7505.573us	1	1	100.00
	i2c_host_perf_precise	5.000s	105.157us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	19.000s	693.976us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	150.762us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	3.000s	526.662us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	579.724us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	545.677us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.000s	309.841us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	1765.877us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	16.816us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	27.625us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	108.903us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	108.903us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	34.556us	1	1	100.00
	i2c_csr_rw	2.000s	80.411us	1	1	100.00
	i2c_csr_aliasing	2.000s	26.248us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	51.387us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	34.556us	1	1	100.00
	i2c_csr_rw	2.000s	80.411us	1	1	100.00
	i2c_csr_aliasing	2.000s	26.248us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	51.387us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	113.083us	1	1	100.00
	i2c_sec_cm	1.000s	142.154us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	113.083us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	22.000s	1585.924us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	301.683us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	8.000s	533.636us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	19070287924932053032311664945878613617557496892503642547984433756517314897083	None
	i2c_target_stress_wr	26322178588630570488266251362187276372299982264363462899736551838464887820757	None
	i2c_target_intr_stress_wr	9129831504568684458744275589124763300452664311680007488988069034759861056530	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	110677498837536211930476805167323526246083526059174476387770936055484419231629	97	UVM_INFO @ 115249063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	9835129161519981652370898770366850291373088954611824330848727640527535884711	127	UVM_INFO @ 48812804214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	15264850786964461127633415026049840524823471367400363394004634117704588100070	90	UVM_INFO @ 5192425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	14414613400525869737894316697384961191822271560605044078590867644059633890759	113	UVM_INFO @ 1585924038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	64281454667404383442520043056449479204010770760531925849039361151952891394684	95	UVM_INFO @ 533636310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	37501357356214408527321169396332980308828513022969678102793737636523344948564	93	UVM_INFO @ 421941259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	73114011797076603235202120203961820570474717153869740485738843186995655367333	87	UVM_INFO @ 301682843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---