Simulation Results: keymgr_dpe/darjeeling

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 55.92 %
  • code
  • 60.36 %
  • assert
  • 96.01 %
  • func
  • 11.38 %
  • block
  • 94.81 %
  • line
  • 95.25 %
  • branch
  • 83.88 %
  • toggle
  • 46.94 %
  • FSM
  • 15.38 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
keymgr_dpe_smoke 5.000s 138.437us 0 1 0.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 2.000s 31.223us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 1.000s 30.343us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 8.000s 905.806us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 5.000s 947.559us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 35.098us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 1.000s 30.343us 1 1 100.00
keymgr_dpe_csr_aliasing 5.000s 947.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 1.000s 40.053us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 1.000s 17.915us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 4.000s 131.056us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 4.000s 131.056us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 2.000s 31.223us 1 1 100.00
keymgr_dpe_csr_rw 1.000s 30.343us 1 1 100.00
keymgr_dpe_csr_aliasing 5.000s 947.559us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.000s 30.075us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 2.000s 31.223us 1 1 100.00
keymgr_dpe_csr_rw 1.000s 30.343us 1 1 100.00
keymgr_dpe_csr_aliasing 5.000s 947.559us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.000s 30.075us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 7.000s 7665.485us 1 1 100.00
keymgr_dpe_tl_intg_err 3.000s 565.643us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_dpe_shadow_reg_errors 2.000s 186.999us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_dpe_shadow_reg_errors 2.000s 186.999us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_dpe_shadow_reg_errors 2.000s 186.999us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_dpe_shadow_reg_errors 2.000s 186.999us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 4.000s 432.704us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 7.000s 7665.485us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 7.000s 7665.485us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert recov_operation_err has unexpected timeout error 1 test run
keymgr_dpe_smoke 8550021692014654085936566678035386173383163487850470289352730329598195473365 1814
UVM_INFO @ 138436605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---