Simulation Results: lc_ctrl/volatile_unlock_enabled

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.08 %
  • code
  • 92.84 %
  • assert
  • 96.54 %
  • func
  • 83.87 %
  • block
  • 97.07 %
  • line
  • 97.63 %
  • branch
  • 92.56 %
  • toggle
  • 85.95 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 179.940us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 58.188us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 43.822us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 234.982us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 100.558us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 133.623us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 43.822us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 100.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 281.259us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 2235.110us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 14.929us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 83.911us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 310.739us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_ctrl_prog_failure 3.000s 83.911us 1 1 100.00
lc_ctrl_errors 4.000s 310.739us 1 1 100.00
lc_ctrl_security_escalation 5.000s 6277.351us 1 1 100.00
lc_ctrl_jtag_state_failure 24.000s 3456.747us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 1065.409us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 1904.139us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 419.849us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 4457.625us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 1065.409us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 1904.139us 1 1 100.00
lc_ctrl_jtag_access 4.000s 604.722us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 1895.353us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 374.991us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 521.041us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 4967.961us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 2400.753us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 92.262us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 298.111us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 288.032us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.000s 237.209us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 16.633us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.000s 2332.312us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 160.850us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 81.105us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 81.105us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 58.188us 1 1 100.00
lc_ctrl_csr_rw 2.000s 43.822us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 100.558us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 444.669us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 58.188us 1 1 100.00
lc_ctrl_csr_rw 2.000s 43.822us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 100.558us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 444.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 792.595us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 53.638us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 53.638us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 2235.110us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_ctrl_sec_cm 3.000s 792.595us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_ctrl_sec_cm 3.000s 792.595us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_ctrl_sec_cm 3.000s 792.595us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_ctrl_sec_cm 3.000s 792.595us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_ctrl_sec_cm 3.000s 792.595us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_ctrl_sec_cm 3.000s 792.595us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_ctrl_sec_cm 3.000s 792.595us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 455.633us 1 1 100.00
lc_ctrl_sec_cm 3.000s 792.595us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 6277.351us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 281.259us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 4457.625us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 770.432us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 770.432us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 1624.699us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 2105.072us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 2105.072us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 8.000s 1140.423us 1 1 100.00