Simulation Results: mbx

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.30 %
  • code
  • 90.92 %
  • assert
  • 97.43 %
  • func
  • 73.54 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 84.15 %
Validation stages
V1
83.33%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 45.000s 21130.655us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 23.521us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 49.678us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 179.704us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 234.931us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 5.339us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 49.678us 1 1 100.00
mbx_csr_aliasing 2.000s 234.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 3.000s 131.831us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 4.000s 635.304us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 53.000s 54694.160us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 8459.773us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 86.970us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 41.422us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 1.378us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 1.378us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 23.521us 1 1 100.00
mbx_csr_rw 1.000s 49.678us 1 1 100.00
mbx_csr_aliasing 2.000s 234.931us 1 1 100.00
mbx_same_csr_outstanding 1.000s 42.033us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 23.521us 1 1 100.00
mbx_csr_rw 1.000s 49.678us 1 1 100.00
mbx_csr_aliasing 2.000s 234.931us 1 1 100.00
mbx_same_csr_outstanding 1.000s 42.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 1390.623us 1 1 100.00
mbx_sec_cm 2.000s 22.367us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 2 test runs
mbx_stress 79570026628608647742490396129363488371749866311057762614248384287698698044771 171
UVM_INFO @ 131831360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 9552374600931158912708162473037279315575134646781560856218824039387210716373 474
UVM_INFO @ 635303612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 36652707439936165384877001320992133600195359550394941581061998055121906163122 85
TL item was: req: (cip_tl_seq_item@17537) { a_addr: 'h5f75a94 a_data: 'hb39068d3 a_mask: 'h5 a_size: 'h2 a_param: 'h0 a_source: 'h4d a_opcode: 'h1 a_user: 'h27a35 d_param: 'h0 d_source: 'h4d d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1377949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 17359962284748816868278637656800331045664891837691840421897491361015429709449 86
TL item was: req: (cip_tl_seq_item@18347) { a_addr: 'h11821a94 a_data: 'hd76bcfad a_mask: 'hb a_size: 'h2 a_param: 'h0 a_source: 'hf3 a_opcode: 'h1 a_user: 'h24834 d_param: 'h0 d_source: 'hf3 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 5339167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---