| V1 |
|
100.00% |
| V2 |
|
85.71% |
| V2S |
|
92.00% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 15.000s | 194.685us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 81.706us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 4.000s | 24.668us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 4.000s | 19.603us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 6.000s | 91.931us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 4.000s | 38.790us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 6.000s | 233.385us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 4.000s | 19.603us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 38.790us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 37.000s | 782.126us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 50.000s | 1253.776us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 32.000s | 302.743us | 1 | 1 | 100.00 | |
| multi_error | 0 | 1 | 0.00 | |||
| otbn_multi_err | 22.000s | 73.592us | 0 | 1 | 0.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 116.000s | 305.151us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 51.000s | 157.997us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 13.000s | 33.472us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 0 | 1 | 0.00 | |||
| otbn_zero_state_err_urnd | 7.000s | 46.560us | 0 | 1 | 0.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 11.000s | 113.235us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 6.000s | 130.888us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 4.000s | 32.104us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 6.000s | 50.983us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 6.000s | 50.983us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 4.000s | 24.668us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 19.603us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 38.790us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 19.263us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 4.000s | 24.668us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 19.603us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 38.790us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 19.263us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 10.000s | 198.575us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 9.000s | 155.829us | 1 | 1 | 100.00 | |
| internal_integrity | 4 | 4 | 100.00 | |||
| otbn_alu_bignum_mod_err | 9.000s | 55.001us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 33.000s | 111.877us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 18.000s | 108.140us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 6.000s | 16.733us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 6.000s | 16.561us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 8.000s | 25.323us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 1 | 1 | 100.00 | |||
| otbn_partial_wipe | 6.000s | 10.266us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| otbn_tl_intg_err | 71.000s | 483.841us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 0 | 1 | 0.00 | |||
| otbn_passthru_mem_tl_intg_err | 15.000s | 48.375us | 0 | 1 | 0.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 15.000s | 194.685us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 9.000s | 155.829us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 10.000s | 198.575us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 71.000s | 483.841us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 13.000s | 33.472us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 10.000s | 198.575us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 9.000s | 155.829us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 7.000s | 46.560us | 0 | 1 | 0.00 | |
| otbn_illegal_mem_acc | 6.000s | 16.561us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 81.706us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 10.000s | 198.575us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 9.000s | 155.829us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 7.000s | 46.560us | 0 | 1 | 0.00 | |
| otbn_illegal_mem_acc | 6.000s | 16.561us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 13.000s | 33.472us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 10.000s | 198.575us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 9.000s | 155.829us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 7.000s | 46.560us | 0 | 1 | 0.00 | |
| otbn_illegal_mem_acc | 6.000s | 16.561us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 81.706us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 7.000s | 58.937us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 7.000s | 21.120us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 32.000s | 102.638us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 32.000s | 102.638us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 17.000s | 236.279us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 8.000s | 54.038us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 15.000s | 52.526us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 15.000s | 52.526us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 14.000s | 62.741us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 81.706us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 81.706us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 81.706us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 116.000s | 305.151us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 81.706us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 81.706us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 10.000s | 22.460us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 81.706us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 300.000s | 1668.800us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_stress_all_with_rand_reset | 203.000s | 581.974us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 8.000s | 22.360us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. | 2 test runs | |||
| otbn_multi_err | 48282817260656120846230821859963140998327167823042274033988185787385361873399 | 254 |
UVM_INFO @ 73592169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_passthru_mem_tl_intg_err | 35099909961515111950045135775662573999990519757960174001569082155508701471099 | 111 |
UVM_INFO @ 48375470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed | 1 test run | |||
| otbn_zero_state_err_urnd | 103615405241362710643783049461689423402006228386619548529618574075675867546215 | 109 |
UVM_ERROR @ 46560026 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 46560026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|