Simulation Results: otp_ctrl

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.57 %
  • code
  • 71.21 %
  • assert
  • 92.01 %
  • func
  • 57.48 %
  • line
  • 87.26 %
  • branch
  • 82.62 %
  • cond
  • 85.73 %
  • toggle
  • 64.35 %
  • FSM
  • 36.09 %
Validation stages
V1
88.89%
V2
70.00%
V2S
44.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.430s 161.056us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 2.380s 295.704us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.430s 159.005us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.770s 47.373us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 9.080s 1160.705us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 8.710s 3310.397us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.170s 87.552us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.770s 47.373us 1 1 100.00
otp_ctrl_csr_aliasing 8.710s 3310.397us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.400s 45.738us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.810s 632.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 108.190s 5256.742us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.330s 681.620us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 2.210s 1035.816us 0 1 0.00
otp_ctrl_check_fail 5.410s 183.316us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.330s 157.700us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 6.690s 764.900us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 10.000s 774.930us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 13.610s 2732.654us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 36.660s 7869.217us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 9.250s 584.961us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 4.620s 669.316us 0 1 0.00
stress_all 1 1 100.00
otp_ctrl_stress_all 54.530s 7435.960us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.540s 165.521us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.830s 199.899us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.280s 83.926us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.280s 83.926us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.430s 159.005us 1 1 100.00
otp_ctrl_csr_rw 1.770s 47.373us 1 1 100.00
otp_ctrl_csr_aliasing 8.710s 3310.397us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.450s 229.929us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.430s 159.005us 1 1 100.00
otp_ctrl_csr_rw 1.770s 47.373us 1 1 100.00
otp_ctrl_csr_aliasing 8.710s 3310.397us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.450s 229.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
otp_ctrl_tl_intg_err 11.480s 1139.480us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.480s 1139.480us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 2.380s 295.704us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 2.380s 295.704us 0 1 0.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
otp_ctrl_macro_errs 9.250s 584.961us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
otp_ctrl_macro_errs 9.250s 584.961us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.160s 1552.927us 1 1 100.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.330s 681.620us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.410s 183.316us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 6.690s 764.900us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 6.690s 764.900us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 6.690s 764.900us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 6.690s 764.900us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 6.690s 764.900us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 2.380s 295.704us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 6.690s 764.900us 0 1 0.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 2.380s 295.704us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 357.440s 200000.000us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.330s 157.700us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 2.380s 295.704us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 2.380s 295.704us 0 1 0.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 9.250s 584.961us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 65.400s 26263.801us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 27.340s 2510.822us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 5 test runs
otp_ctrl_background_chks 115716135651734814132048648246314233060578412529864834934832519519506425782337 914
UVM_INFO @ 1035816438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 8776088723214659700734997722980547241141772618388875669674630131376227032032 6633
UVM_INFO @ 764899572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 37708214057866084587295352736651790914155783399529926640754226578888374654584 5230
UVM_INFO @ 584961281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 59312935401833771979909775827043085562590642232917796854105979240493224447581 2468
UVM_INFO @ 669316115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79832325086393787800293112700788484198319385280658803535042340683427713078196 11316
UVM_INFO @ 2510822406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_smoke 21213697934621596053228994705731672649110926762911847710103498708980201218818 300
UVM_INFO @ 295703883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_partition_walk 44210139553898088954940060559748736591649872383317723965494817746714727638801 160055
UVM_INFO @ 5256741845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 74877915681861108647635296997750652558014827858148131752126456014383832482404 89
UVM_INFO @ 26263801423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 101838755561338776670242947312493896993048425051279712664356763207667583599281 3974
UVM_INFO @ 183316203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
otp_ctrl_sec_cm 55971017893929819577942895766300839492982130705586229081469034027205911683959 2375
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---