Simulation Results: rom_ctrl/64kb

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.85 %
  • code
  • 83.31 %
  • assert
  • 97.38 %
  • func
  • 97.86 %
  • block
  • 86.94 %
  • line
  • 86.21 %
  • branch
  • 86.11 %
  • toggle
  • 84.74 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 730.160us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 79.922us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 60.927us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 124.602us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 58.069us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 61.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 60.927us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 58.069us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 52.538us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 61.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 329.054us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.000s 2102.843us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 109.112us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 51.784us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 222.665us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 222.665us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 79.922us 1 1 100.00
rom_ctrl_csr_rw 3.000s 60.927us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 58.069us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 66.237us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 79.922us 1 1 100.00
rom_ctrl_csr_rw 3.000s 60.927us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 58.069us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 66.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 107.147us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 194.000s 551.227us 1 1 100.00
rom_ctrl_tl_intg_err 41.000s 648.153us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 194.000s 551.227us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 194.000s 551.227us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.000s 551.227us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 194.000s 551.227us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 730.160us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 730.160us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 730.160us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 41.000s 648.153us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
rom_ctrl_kmac_err_chk 3.000s 109.112us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 4.667us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 107.147us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.000s 551.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 47.000s 13891.420us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 691715424159589617880721161373819383169424790765453697744829652603866503513 88
UVM_INFO @ 329053532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:278) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 57594742593915337191533983211430542370747779169215305318463197441380293629816 87
UVM_INFO @ 4666799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---