Simulation Results: rstmgr

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.15 %
  • code
  • 99.30 %
  • assert
  • 98.17 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.75 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.200s 73.761us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.290s 92.171us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.190s 37.307us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.600s 81.635us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.550s 43.594us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.040s 67.406us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.190s 37.307us 1 1 100.00
rstmgr_csr_aliasing 1.550s 43.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.050s 104.548us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.160s 49.476us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.900s 49.140us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.550s 437.175us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.550s 437.175us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.550s 437.175us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.550s 437.175us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 35.230s 5770.114us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.980s 40.802us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.990s 47.601us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.990s 47.601us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.290s 92.171us 1 1 100.00
rstmgr_csr_rw 1.190s 37.307us 1 1 100.00
rstmgr_csr_aliasing 1.550s 43.594us 1 1 100.00
rstmgr_same_csr_outstanding 1.150s 45.599us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.290s 92.171us 1 1 100.00
rstmgr_csr_rw 1.190s 37.307us 1 1 100.00
rstmgr_csr_aliasing 1.550s 43.594us 1 1 100.00
rstmgr_same_csr_outstanding 1.150s 45.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 30.580s 6754.215us 1 1 100.00
rstmgr_tl_intg_err 2.350s 344.357us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 30.580s 6754.215us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 30.580s 6754.215us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.350s 344.357us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.200s 62.613us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.450s 433.914us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.230s 292.259us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 30.580s 6754.215us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.190s 37.307us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.190s 37.307us 1 1 100.00