Simulation Results

Simulation Results: rv_dm/use_dmi_interface

03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.65 %

code
74.12 %

assert
96.59 %

func
92.24 %

block
89.58 %

line
89.47 %

branch
71.71 %

toggle
72.81 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	32.000s	2551.717us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	31.000s	288.749us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	877.378us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	73.000s	38699.898us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	32.000s	913.587us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	37.000s	2922.410us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	35.000s	4538.994us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	35.000s	2866.174us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	60.000s	68680.980us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	29.000s	217.013us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	33.000s	257.400us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	235.811us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	33.000s	335.591us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	31.000s	299.869us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	32.000s	627.912us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	35.000s	104.952us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	32.000s	334.801us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	29.000s	217.013us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	30.000s	183.076us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	30.000s	266.527us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	235.811us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	30.000s	127.031us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	31.000s	315.640us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	34.000s	52.504us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	48.000s	9623.797us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	47.000s	2113.059us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	33.000s	200.269us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	47.000s	2113.059us	1	1	100.00
	rv_dm_csr_rw	34.000s	52.504us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	122.132us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	30.000s	120.994us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	32.000s	2551.717us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	31.000s	183.755us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	31.000s	124.054us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	32.000s	302.353us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	31.000s	506.742us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	52.000s	12888.478us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	32.000s	83.028us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	35.000s	2656.352us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	30.000s	80.224us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	34.000s	686.009us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	31.000s	797.036us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	30.000s	285.894us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	32.000s	111.425us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	34.000s	8728.718us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	60.000s	16380.366us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	89.049us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	29.000s	168.259us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	31.000s	92.194us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	169.517us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	169.517us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	47.000s	2113.059us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	315.640us	1	1	100.00
	rv_dm_csr_rw	34.000s	52.504us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	518.068us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	47.000s	2113.059us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	315.640us	1	1	100.00
	rv_dm_csr_rw	34.000s	52.504us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	518.068us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	30.000s	656.685us	1	1	100.00
	rv_dm_tl_intg_err	39.000s	5298.637us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	39.000s	5298.637us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	797.036us	1	1	100.00
	rv_dm_debug_disabled	32.000s	184.234us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	797.036us	1	1	100.00
	rv_dm_debug_disabled	32.000s	184.234us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	32.000s	2551.717us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	30.000s	258.283us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	121.235us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	121.235us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	30.000s	258.283us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	64.000s	2345.231us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	385.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	32184934815701625009587038687180229934044946868763836892411544395768490077560	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23810
	rv_dm_bad_sba_tl_access	7821989410389813108183677151035806469794054801949473204011189489736451754461	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23818
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	18946592928996545585410232936377932998612648787570625585551346656581376214703	107	UVM_INFO @ 83028329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	104431154156395031209964673870656315833438533382434507208202345269428201747218	107	UVM_INFO @ 80224400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	61161127654972016652994477205015247612977031506446673719677955042708548637723	87	UVM_INFO @ 335591376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	93824274176716417781976977094962136949489511017116008761332373676301361088815	88	UVM_INFO @ 168259277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	115490031460855819077476313546732738855464875173677983022413301411864539884807	87	UVM_INFO @ 111425012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	5092313286803410503672330661890846829711143132949200280593769601803992956664	87	UVM_INFO @ 686008593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	58178324037009985099310473738872568889045042784211123831032202119114375818984	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				1 test run
	rv_dm_stress_all_with_rand_reset	34093678413067029024879675502030284154682405832057341002206455967484250494684	149	UVM_INFO @ 2345231233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---