Simulation Results: rv_timer

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.37 %
  • code
  • 90.45 %
  • assert
  • 97.78 %
  • func
  • 97.88 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 67.756us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 2.000s 69.021us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 2.000s 11.633us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 603.122us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 23.378us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 31.921us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 2.000s 11.633us 1 1 100.00
rv_timer_csr_aliasing 1.000s 23.378us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.000s 140.645us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 3872.460us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 2.000s 44.191us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 2.000s 44.191us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 565.864us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 12.637us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 2.000s 18.720us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.000s 51.210us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.000s 51.210us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 69.021us 1 1 100.00
rv_timer_csr_rw 2.000s 11.633us 1 1 100.00
rv_timer_csr_aliasing 1.000s 23.378us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 33.093us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 69.021us 1 1 100.00
rv_timer_csr_rw 2.000s 11.633us 1 1 100.00
rv_timer_csr_aliasing 1.000s 23.378us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 33.093us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 376.789us 1 1 100.00
rv_timer_tl_intg_err 2.000s 315.212us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 315.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 1.000s 16.390us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 2.000s 42.901us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 22.000s 4789.303us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 3172924951707380948447423044614116992575247014084335234033539467907638943945 84
UVM_INFO @ 42900756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 103876163832679787127511072611015253687896111616036624700731612114357303764352 84
UVM_INFO @ 140645315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---