Simulation Results: spi_device/1r1w

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.23 %
  • code
  • 89.54 %
  • assert
  • 95.40 %
  • func
  • 70.76 %
  • block
  • 98.38 %
  • line
  • 98.78 %
  • branch
  • 97.06 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 139.000s 137238.534us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 132.034us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 296.019us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 13.000s 1944.615us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.000s 758.268us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 461.562us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 296.019us 1 1 100.00
spi_device_csr_aliasing 14.000s 758.268us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 20.828us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 36.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 16.678us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 10.001us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.627us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 48.453us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 48.453us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.000s 277.224us 1 1 100.00
spi_device_tpm_sts_read 2.000s 156.771us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 31.000s 3012.175us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 23.000s 4170.045us 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.000s 785.232us 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.000s 785.232us 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 9.000s 1653.532us 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 9.000s 1653.532us 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 9.000s 1653.532us 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 9.000s 1653.532us 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 9.000s 1653.532us 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 25.000s 3112.513us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 14.000s 2715.795us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 14.000s 2715.795us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 14.000s 2715.795us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.000s 609.633us 1 1 100.00
spi_device_read_buffer_direct 4.000s 2874.853us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 14.000s 2715.795us 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 22.000s 2826.575us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 134.687us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 134.687us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 366.000s 94186.486us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 139.000s 137238.534us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 188.000s 16897.755us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 2.000s 335.368us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 14.750us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 29.802us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 5.000s 73.780us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 5.000s 73.780us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 132.034us 1 1 100.00
spi_device_csr_rw 3.000s 296.019us 1 1 100.00
spi_device_csr_aliasing 14.000s 758.268us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 343.215us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 132.034us 1 1 100.00
spi_device_csr_rw 3.000s 296.019us 1 1 100.00
spi_device_csr_aliasing 14.000s 758.268us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 343.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 96.036us 1 1 100.00
spi_device_tl_intg_err 10.000s 750.120us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 10.000s 750.120us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 101332176284978864652789495184442164923764208347483787846501205693086245825113 87
UVM_ERROR @ 7923799 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[943] not found within the scope .
UVM_ERROR @ 7923799 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[943] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 95535016966739717657877752510785308550382873231566464282210215628967642835656 85
UVM_ERROR @ 938935 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x79 [1111001] vs 0x0 [0])
UVM_ERROR @ 979935 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3b [111011] vs 0x0 [0])
UVM_ERROR @ 1032935 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc2 [11000010] vs 0x0 [0])
UVM_ERROR @ 1082935 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1de [111011110] vs 0x0 [0])