Simulation Results: uart

 
03/08/2026 19:51:35 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.44 %
  • code
  • 73.64 %
  • assert
  • 97.98 %
  • func
  • 90.69 %
  • block
  • 98.58 %
  • line
  • 99.24 %
  • branch
  • 97.24 %
  • toggle
  • 73.08 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 4.000s 891.056us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 2.000s 1070.358us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 27.057us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 1282.360us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 19.475us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 20.419us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 27.057us 1 1 100.00
uart_csr_aliasing 2.000s 19.475us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 12.000s 7765.842us 1 1 100.00
parity 2 2 100.00
uart_smoke 4.000s 891.056us 1 1 100.00
uart_tx_rx 12.000s 7765.842us 1 1 100.00
parity_error 2 2 100.00
uart_intr 99.000s 87930.590us 1 1 100.00
uart_rx_parity_err 50.000s 74398.553us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 12.000s 7765.842us 1 1 100.00
uart_intr 99.000s 87930.590us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 40.000s 57394.387us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 15.000s 11392.271us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 29.000s 22938.849us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 99.000s 87930.590us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 99.000s 87930.590us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 99.000s 87930.590us 1 1 100.00
perf 1 1 100.00
uart_perf 32.000s 14776.734us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 8.000s 4152.288us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 8.000s 4152.288us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 8.000s 21810.865us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.000s 4482.267us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 11.000s 7232.827us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 10.000s 2905.204us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 239.000s 120964.770us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 1.000s 649.585us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 1.000s 10.501us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 26.736us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 94.519us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 94.519us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 2.000s 1070.358us 1 1 100.00
uart_csr_rw 1.000s 27.057us 1 1 100.00
uart_csr_aliasing 2.000s 19.475us 1 1 100.00
uart_same_csr_outstanding 1.000s 18.163us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 2.000s 1070.358us 1 1 100.00
uart_csr_rw 1.000s 27.057us 1 1 100.00
uart_csr_aliasing 2.000s 19.475us 1 1 100.00
uart_same_csr_outstanding 1.000s 18.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 3616.910us 1 1 100.00
uart_tl_intg_err 2.000s 117.419us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 117.419us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 33.000s 16488.566us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 45700269134268869395966175353478212906997680323092485777734834285871368717244 88
UVM_ERROR @ 16857573343 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 16857640010 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (203 [0xcb] vs 223 [0xdf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 17086574488 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 17086707822 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_stress_all 17246199792249692894317866338228336624004210379141491962017466666678521455076 84
UVM_ERROR @ 68288252 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 68288252 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 294998399 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 294998399 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr