Simulation Results: ac_range_check

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.07 %
  • code
  • 93.18 %
  • assert
  • 97.75 %
  • func
  • 58.28 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.36 %
Validation stages
V1
85.71%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 0 1 0.00
ac_range_check_smoke 23.000s 4664.433us 0 1 0.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 40.000s 4999.033us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 38.097us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 437.458us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 21.000s 710.280us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 18.000s 1178.737us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 1.000s 59.152us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 437.458us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 1178.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 82.370us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 19.000s 3509.358us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 116.000s 5334.056us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 30.912us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 24.464us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 1542.834us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 1542.834us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 38.097us 1 1 100.00
ac_range_check_csr_rw 2.000s 437.458us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 1178.737us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 234.813us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 38.097us 1 1 100.00
ac_range_check_csr_rw 2.000s 437.458us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 1178.737us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 234.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 3935.590us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 3935.590us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 3935.590us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 3935.590us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 57.000s 2796.124us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 63.156us 1 1 100.00
ac_range_check_tl_intg_err 6.000s 120.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 326.000s 7323.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 24.000s 1333.245us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 1 test run
ac_range_check_smoke 110573162512898601576133710928832347638873597408605416532715276566100053104493 4462
UVM_INFO @ 4664432975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---