Simulation Results: aes/gcm_unmasked

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.42 %
  • code
  • 90.64 %
  • assert
  • 97.75 %
  • func
  • 61.88 %
  • block
  • 90.90 %
  • line
  • 92.36 %
  • branch
  • 83.54 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 78.489us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 79.366us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 63.487us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 88.933us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 3386.916us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 157.260us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 107.026us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 88.933us 1 1 100.00
aes_csr_aliasing 2.000s 157.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 79.366us 1 1 100.00
aes_config_error 2.000s 80.304us 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 79.366us 1 1 100.00
aes_config_error 2.000s 80.304us 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 135.591us 1 1 100.00
aes_b2b 4.000s 238.219us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 79.366us 1 1 100.00
aes_config_error 2.000s 80.304us 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
aes_alert_reset 2.000s 116.045us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 57.528us 1 1 100.00
aes_config_error 2.000s 80.304us 1 1 100.00
aes_alert_reset 2.000s 116.045us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 53.513us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 959.786us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 116.045us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 135.591us 1 1 100.00
aes_sideload 3.000s 73.453us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 103.796us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.086s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 53.144us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 198.862us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 198.862us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.487us 1 1 100.00
aes_csr_rw 2.000s 88.933us 1 1 100.00
aes_csr_aliasing 2.000s 157.260us 1 1 100.00
aes_same_csr_outstanding 2.000s 280.198us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.487us 1 1 100.00
aes_csr_rw 2.000s 88.933us 1 1 100.00
aes_csr_aliasing 2.000s 157.260us 1 1 100.00
aes_same_csr_outstanding 2.000s 280.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 114.671us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 111.769us 0 1 0.00
aes_control_fi 2.000s 49.169us 1 1 100.00
aes_cipher_fi 1.000s 59.169us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 85.670us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 85.670us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 85.670us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 85.670us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 157.745us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 1246.754us 1 1 100.00
aes_tl_intg_err 2.000s 120.753us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 120.753us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 116.045us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 85.670us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 85.670us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 79.366us 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
aes_alert_reset 2.000s 116.045us 1 1 100.00
aes_core_fi 2.000s 216.494us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 80.304us 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
aes_core_fi 2.000s 216.494us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 85.670us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 296.387us 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 135.591us 1 1 100.00
aes_sideload 3.000s 73.453us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 296.387us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 296.387us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 296.387us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 296.387us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 296.387us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 135.591us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 111.769us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 111.769us 0 1 0.00
aes_control_fi 2.000s 49.169us 1 1 100.00
aes_cipher_fi 1.000s 59.169us 1 1 100.00
aes_ctr_fi 2.000s 52.072us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 111.769us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 111.769us 0 1 0.00
aes_control_fi 2.000s 49.169us 1 1 100.00
aes_cipher_fi 1.000s 59.169us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 59.169us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 111.769us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 111.769us 0 1 0.00
aes_control_fi 2.000s 49.169us 1 1 100.00
aes_ctr_fi 2.000s 52.072us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 111.769us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 111.769us 0 1 0.00
aes_control_fi 2.000s 49.169us 1 1 100.00
aes_cipher_fi 1.000s 59.169us 1 1 100.00
aes_ctr_fi 2.000s 52.072us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 116.045us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 111.769us 0 1 0.00
aes_control_fi 2.000s 49.169us 1 1 100.00
aes_cipher_fi 1.000s 59.169us 1 1 100.00
aes_ctr_fi 2.000s 52.072us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 111.769us 0 1 0.00
aes_control_fi 2.000s 49.169us 1 1 100.00
aes_cipher_fi 1.000s 59.169us 1 1 100.00
aes_ctr_fi 2.000s 52.072us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 111.769us 0 1 0.00
aes_control_fi 2.000s 49.169us 1 1 100.00
aes_ctr_fi 2.000s 52.072us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 111.769us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 111.769us 0 1 0.00
aes_control_fi 2.000s 49.169us 1 1 100.00
aes_cipher_fi 1.000s 59.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 6.000s 700.600us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 24932089598287857757485122709853536144630632353607983458092072982829139648024 3763
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_stress_all 99765897739104565795477100655657078825616690594145271120322561963974750844999 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 58186189803202743865556239663616036293448667521230904326726678914373339577903 223
UVM_INFO @ 700600460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---