Simulation Results: alert_handler

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.28 %
  • code
  • 89.05 %
  • assert
  • 98.02 %
  • func
  • 77.76 %
  • line
  • 99.64 %
  • branch
  • 98.34 %
  • cond
  • 91.33 %
  • toggle
  • 84.97 %
  • FSM
  • 70.97 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 31.900s 2533.120us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 9.000s 132.421us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.570s 44.896us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 207.670s 5532.399us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 205.320s 8095.247us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.160s 246.796us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.570s 44.896us 1 1 100.00
alert_handler_csr_aliasing 205.320s 8095.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 42.430s 779.123us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 8.010s 182.830us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1320.440s 76789.284us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 19.300s 484.117us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 31.900s 2533.120us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 9.080s 255.991us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 29.760s 488.228us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 7.800s 1045.461us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1596.080s 25062.398us 1 1 100.00
alert_handler_lpg_stub_clk 1906.000s 45636.845us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 549.450s 199195.188us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 4.190s 77.493us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.350s 17.768us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.360s 12.848us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 14.460s 552.093us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 14.460s 552.093us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 9.000s 132.421us 1 1 100.00
alert_handler_csr_rw 4.570s 44.896us 1 1 100.00
alert_handler_csr_aliasing 205.320s 8095.247us 1 1 100.00
alert_handler_same_csr_outstanding 9.610s 395.561us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 9.000s 132.421us 1 1 100.00
alert_handler_csr_rw 4.570s 44.896us 1 1 100.00
alert_handler_csr_aliasing 205.320s 8095.247us 1 1 100.00
alert_handler_same_csr_outstanding 9.610s 395.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 150.130s 2847.775us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 150.130s 2847.775us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 150.130s 2847.775us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 150.130s 2847.775us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 988.750s 16954.055us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
alert_handler_tl_intg_err 37.160s 706.184us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 37.160s 706.184us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 150.130s 2847.775us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 31.900s 2533.120us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 31.900s 2533.120us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 31.900s 2533.120us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 31.900s 2533.120us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 19.300s 484.117us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1596.080s 25062.398us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 19.300s 484.117us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1320.440s 76789.284us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1320.440s 76789.284us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 22.850s 1804.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 21.320s 547.216us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. 1 test run
alert_handler_ping_timeout 63721198433855603567916823401978419523460863603572426676168708362072995751729 81
UVM_INFO @ 1045460709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 43932205917398455634488589167330534345764572202267302713361362779099089564882 170
UVM_INFO @ 77493338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 15700226385155077672613626823688718043692748239646411375599616049262106295647 90
UVM_INFO @ 547215731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---