Simulation Results: clkmgr

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.29 %
  • code
  • 69.56 %
  • assert
  • 89.67 %
  • func
  • 69.65 %
  • line
  • 82.37 %
  • branch
  • 87.31 %
  • cond
  • 78.33 %
  • toggle
  • 99.81 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
69.23%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 2.060s 177.295us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.150s 32.267us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.140s 60.624us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 5.030s 471.122us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.570s 98.335us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.700s 4.195us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.140s 60.624us 1 1 100.00
clkmgr_csr_aliasing 1.570s 98.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.130s 31.366us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.580s 106.698us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.970s 15.174us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 2.060s 177.295us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.700s 6.951us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.700s 3.751us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.700s 6.951us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.490s 98.260us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.810s 18.220us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.930s 40.619us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.930s 40.619us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 1.150s 32.267us 1 1 100.00
clkmgr_csr_rw 1.140s 60.624us 1 1 100.00
clkmgr_csr_aliasing 1.570s 98.335us 1 1 100.00
clkmgr_same_csr_outstanding 0.680s 4.391us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 1.150s 32.267us 1 1 100.00
clkmgr_csr_rw 1.140s 60.624us 1 1 100.00
clkmgr_csr_aliasing 1.570s 98.335us 1 1 100.00
clkmgr_same_csr_outstanding 0.680s 4.391us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 8.140s 877.139us 1 1 100.00
clkmgr_tl_intg_err 0.870s 25.861us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 0.950s 30.558us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 0.950s 30.558us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 0.950s 30.558us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 0.950s 30.558us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.750s 8.513us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.870s 25.861us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.700s 6.951us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.700s 3.751us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 0.950s 30.558us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.340s 79.598us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.140s 60.624us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 8.140s 877.139us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.140s 60.624us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.140s 60.624us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 8.140s 877.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.700s 1.212us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.210s 36.432us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 93158530008873453147791228773089361423454157348699946846801310814640795514948 76
UVM_INFO @ 6951367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 29888598888866657668838557822520624587626455982698747189833516838559908885522 81
UVM_INFO @ 36431705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 16554423064811954948650216593073370802524528929281047541565489432671063779504 76
UVM_INFO @ 98260219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 41328706293981016670501731184318669212450407957485771287724159546561319054446 75
UVM_INFO @ 8513138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 46887795062102591356110861242196908734795287602248777589223469990495080958517 86
UVM_INFO @ 25860855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 47593985310960978932399058902650887847428915609001423468445333728064064448385 76
UVM_INFO @ 4194948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 19455064072924701106491849312305608163272886670613457790741648108587914055104 78
UVM_INFO @ 3750881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 6677968546673388108609157398391481689404548112385955401719461812968563347745 74
UVM_INFO @ 1212462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 56040301484970655672851190456330267005242984528295843028426287391100689962578 75
UVM_INFO @ 471121821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 68974959678009580296774643577726694793070233736756067587997967867277224436921 75
UVM_INFO @ 4391001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---