Simulation Results: csrng

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.96 %
  • code
  • 94.65 %
  • assert
  • 94.54 %
  • func
  • 74.68 %
  • block
  • 96.95 %
  • line
  • 97.69 %
  • branch
  • 92.43 %
  • toggle
  • 93.24 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 133.336us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 17.707us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 39.825us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 31.000s 2250.761us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 32.321us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 29.464us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 39.825us 1 1 100.00
csrng_csr_aliasing 2.000s 32.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 246.778us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 4.000s 73.625us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 4.000s 73.625us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 1434.000s 148007.202us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 51.666us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 29.329us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 102.778us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 102.778us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 17.707us 1 1 100.00
csrng_csr_rw 1.000s 39.825us 1 1 100.00
csrng_csr_aliasing 2.000s 32.321us 1 1 100.00
csrng_same_csr_outstanding 2.000s 52.615us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 17.707us 1 1 100.00
csrng_csr_rw 1.000s 39.825us 1 1 100.00
csrng_csr_aliasing 2.000s 32.321us 1 1 100.00
csrng_same_csr_outstanding 2.000s 52.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 11.000s 393.602us 1 1 100.00
csrng_tl_intg_err 4.000s 112.651us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 85.446us 1 1 100.00
csrng_csr_rw 1.000s 39.825us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 246.778us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 1434.000s 148007.202us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
csrng_sec_cm 11.000s 393.602us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
csrng_sec_cm 11.000s 393.602us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
csrng_sec_cm 11.000s 393.602us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
csrng_sec_cm 11.000s 393.602us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
csrng_sec_cm 11.000s 393.602us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 246.778us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 1434.000s 148007.202us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 246.778us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 112.651us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
csrng_sec_cm 11.000s 393.602us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
csrng_sec_cm 11.000s 393.602us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 191.987us 1 1 100.00
csrng_err 1.000s 20.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 33464224066792230983720883995441634885235679594160530072323269879410857750583 110
UVM_INFO @ 73624686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 7343144420633759348977374464603856156990035557767546598125984884195261609864 None