Simulation Results: edn/edn0

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 78.56 %
  • code
  • 87.68 %
  • assert
  • 96.68 %
  • func
  • 51.33 %
  • block
  • 94.90 %
  • line
  • 97.46 %
  • branch
  • 88.97 %
  • toggle
  • 76.68 %
  • FSM
  • 87.60 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 20.147us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 29.942us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 55.191us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 145.377us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 3.000s 40.354us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 34.128us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 55.191us 1 1 100.00
edn_csr_aliasing 3.000s 40.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 74.106us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 74.106us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 74.106us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 21.446us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 23.673us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 25.800us 1 1 100.00
disable 2 2 100.00
edn_disable 6.000s 43.460us 1 1 100.00
edn_disable_auto_req_mode 3.000s 58.032us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 88.808us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 16.488us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 26.268us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 367.057us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 367.057us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 29.942us 1 1 100.00
edn_csr_rw 1.000s 55.191us 1 1 100.00
edn_csr_aliasing 3.000s 40.354us 1 1 100.00
edn_same_csr_outstanding 1.000s 19.317us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 29.942us 1 1 100.00
edn_csr_rw 1.000s 55.191us 1 1 100.00
edn_csr_aliasing 3.000s 40.354us 1 1 100.00
edn_same_csr_outstanding 1.000s 19.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 9.000s 677.721us 1 1 100.00
edn_tl_intg_err 3.000s 138.343us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 26.415us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 23.673us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.000s 677.721us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.000s 677.721us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 9.000s 677.721us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 9.000s 677.721us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 23.673us 1 1 100.00
edn_sec_cm 9.000s 677.721us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 23.673us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 138.343us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 49.000s 2564.351us 1 1 100.00