Simulation Results: edn/edn1

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.84 %
  • code
  • 84.78 %
  • assert
  • 98.70 %
  • func
  • 80.04 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 89.08 %
  • toggle
  • 95.64 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.020s 27.644us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 16.989us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 13.812us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.820s 316.645us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.260s 37.262us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.490s 57.610us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 13.812us 1 1 100.00
edn_csr_aliasing 1.260s 37.262us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.710s 479.647us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.710s 479.647us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.710s 479.647us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.990s 24.359us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.290s 329.692us 1 1 100.00
errs 1 1 100.00
edn_err 1.130s 37.430us 1 1 100.00
disable 2 2 100.00
edn_disable 0.690s 104.222us 1 1 100.00
edn_disable_auto_req_mode 1.130s 78.038us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.040s 216.112us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.930s 33.304us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 32.694us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.990s 243.838us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.990s 243.838us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 16.989us 1 1 100.00
edn_csr_rw 0.810s 13.812us 1 1 100.00
edn_csr_aliasing 1.260s 37.262us 1 1 100.00
edn_same_csr_outstanding 1.220s 76.086us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 16.989us 1 1 100.00
edn_csr_rw 0.810s 13.812us 1 1 100.00
edn_csr_aliasing 1.260s 37.262us 1 1 100.00
edn_same_csr_outstanding 1.220s 76.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.820s 399.537us 1 1 100.00
edn_tl_intg_err 1.510s 117.050us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 31.734us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.290s 329.692us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.820s 399.537us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.820s 399.537us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.820s 399.537us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.820s 399.537us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.290s 329.692us 1 1 100.00
edn_sec_cm 2.820s 399.537us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.290s 329.692us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.510s 117.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 28.510s 2673.990us 1 1 100.00