Simulation Results: entropy_src/rng_16bits

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 70.22 %
  • code
  • 83.10 %
  • assert
  • 74.20 %
  • func
  • 53.36 %
  • block
  • 94.24 %
  • line
  • 97.90 %
  • branch
  • 86.36 %
  • toggle
  • 52.32 %
  • FSM
  • 95.83 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 27.876us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 21.591us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 68.794us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 9.000s 6662.453us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 6.000s 971.616us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 231.714us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 68.794us 1 1 100.00
entropy_src_csr_aliasing 6.000s 971.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 27.876us 1 1 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
entropy_src_fw_ov 378.000s 14062.259us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 378.000s 14062.259us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 401.000s 13019.896us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
entropy_src_intr 22.000s 6295.711us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
entropy_src_functional_alerts 6.000s 349.262us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 308.000s 14290.410us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 31.635us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 9.000s 168.149us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 16.061us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 93.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 452.433us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 452.433us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 21.591us 1 1 100.00
entropy_src_csr_rw 2.000s 68.794us 1 1 100.00
entropy_src_csr_aliasing 6.000s 971.616us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 97.463us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 21.591us 1 1 100.00
entropy_src_csr_rw 2.000s 68.794us 1 1 100.00
entropy_src_csr_aliasing 6.000s 971.616us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 97.463us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 368.556us 1 1 100.00
entropy_src_tl_intg_err 5.000s 177.541us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
entropy_src_cfg_regwen 2.000s 63.671us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
entropy_src_fw_ov 378.000s 14062.259us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 31.635us 1 1 100.00
entropy_src_sec_cm 2.000s 368.556us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 31.635us 1 1 100.00
entropy_src_sec_cm 2.000s 368.556us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 80.000s 13159.954us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 31.635us 1 1 100.00
entropy_src_sec_cm 2.000s 368.556us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 31.635us 1 1 100.00
entropy_src_sec_cm 2.000s 368.556us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 31.635us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 349.262us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 5.000s 177.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 44.000s 13113.701us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 3.000s 9.268us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 48199305528590889235106334978454945056067570656400553897061130704418470552223 114
UVM_INFO @ 9267564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 41154182326982948298155212696953823482451610439026449758556410906019971916272 113
UVM_INFO @ 231714456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---