Simulation Results: hmac

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.10 %
  • code
  • 95.91 %
  • assert
  • 97.17 %
  • func
  • 29.21 %
  • block
  • 97.41 %
  • line
  • 98.35 %
  • branch
  • 93.52 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 5.000s 485.658us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 140.628us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 16.208us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.000s 934.004us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 800.068us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 32.479us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 16.208us 1 1 100.00
hmac_csr_aliasing 3.000s 800.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 6.000s 392.094us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 19.000s 1128.394us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 244.030us 1 1 100.00
hmac_test_sha384_vectors 361.000s 147650.421us 1 1 100.00
hmac_test_sha512_vectors 354.000s 32983.768us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 807.694us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 4684.971us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 491.059us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 29.000s 962.137us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 47.000s 2772.526us 1 1 100.00
error 1 1 100.00
hmac_error 7.000s 3048.259us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 8.000s 686.480us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 5.000s 485.658us 1 1 100.00
hmac_long_msg 6.000s 392.094us 1 1 100.00
hmac_back_pressure 19.000s 1128.394us 1 1 100.00
hmac_datapath_stress 47.000s 2772.526us 1 1 100.00
hmac_burst_wr 29.000s 962.137us 1 1 100.00
hmac_stress_all 191.000s 109431.818us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 5.000s 485.658us 1 1 100.00
hmac_long_msg 6.000s 392.094us 1 1 100.00
hmac_back_pressure 19.000s 1128.394us 1 1 100.00
hmac_datapath_stress 47.000s 2772.526us 1 1 100.00
hmac_wipe_secret 8.000s 686.480us 1 1 100.00
hmac_test_sha256_vectors 10.000s 244.030us 1 1 100.00
hmac_test_sha384_vectors 361.000s 147650.421us 1 1 100.00
hmac_test_sha512_vectors 354.000s 32983.768us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 807.694us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 4684.971us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 491.059us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 5.000s 485.658us 1 1 100.00
hmac_long_msg 6.000s 392.094us 1 1 100.00
hmac_back_pressure 19.000s 1128.394us 1 1 100.00
hmac_datapath_stress 47.000s 2772.526us 1 1 100.00
hmac_burst_wr 29.000s 962.137us 1 1 100.00
hmac_error 7.000s 3048.259us 1 1 100.00
hmac_wipe_secret 8.000s 686.480us 1 1 100.00
hmac_test_sha256_vectors 10.000s 244.030us 1 1 100.00
hmac_test_sha384_vectors 361.000s 147650.421us 1 1 100.00
hmac_test_sha512_vectors 354.000s 32983.768us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 807.694us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 4684.971us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 491.059us 1 1 100.00
hmac_stress_all 191.000s 109431.818us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 191.000s 109431.818us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 12.133us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 21.856us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 255.006us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 255.006us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 140.628us 1 1 100.00
hmac_csr_rw 2.000s 16.208us 1 1 100.00
hmac_csr_aliasing 3.000s 800.068us 1 1 100.00
hmac_same_csr_outstanding 2.000s 86.545us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 140.628us 1 1 100.00
hmac_csr_rw 2.000s 16.208us 1 1 100.00
hmac_csr_aliasing 3.000s 800.068us 1 1 100.00
hmac_same_csr_outstanding 2.000s 86.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 177.722us 1 1 100.00
hmac_tl_intg_err 6.000s 525.861us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 6.000s 525.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 5.000s 485.658us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.000s 428.183us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 61.000s 34472.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 70.655us 1 1 100.00