Simulation Results

Simulation Results: i2c

04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.96 %

code
85.71 %

assert
97.46 %

func
80.72 %

block
95.98 %

line
95.37 %

branch
92.78 %

toggle
72.68 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	249.000s	21637.045us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.000s	4105.713us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	20.829us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	29.243us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	7.000s	2320.238us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	62.279us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	28.022us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	29.243us	1	1	100.00
	i2c_csr_aliasing	2.000s	62.279us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	6.826us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	409.000s	26570.243us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	1724.000s	6592.310us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	47.050us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	3379.000s	3041.668us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	2349.000s	9820.372us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	217.973us	1	1	100.00
	i2c_host_fifo_fmt_empty	98.000s	452.669us	1	1	100.00
	i2c_host_fifo_reset_rx	6.000s	179.881us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	692.000s	10953.645us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	12.000s	1573.580us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	4.000s	147.304us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	1373.759us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	7.000s	905.201us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	27.000s	1661.182us	1	1	100.00
	i2c_target_intr_smoke	7.000s	3723.302us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	132.435us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	165.979us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	10.000s	7850.922us	1	1	100.00
	i2c_target_stress_rd	27.000s	1661.182us	1	1	100.00
	i2c_target_intr_stress_wr	3601.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.000s	1363.991us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	43.000s	2490.702us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	3579.095us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	27.000s	10076.369us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	609.441us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	125.966us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	1724.000s	6592.310us	1	1	100.00
	i2c_host_perf_precise	10.000s	325.828us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	12.000s	1573.580us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	139.889us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	2416.020us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	531.026us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	137.430us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	13.000s	607.691us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	3671.348us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	19.348us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	32.769us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	41.890us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	41.890us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	20.829us	1	1	100.00
	i2c_csr_rw	1.000s	29.243us	1	1	100.00
	i2c_csr_aliasing	2.000s	62.279us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	151.648us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	20.829us	1	1	100.00
	i2c_csr_rw	1.000s	29.243us	1	1	100.00
	i2c_csr_aliasing	2.000s	62.279us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	151.648us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	140.686us	1	1	100.00
	i2c_sec_cm	2.000s	179.965us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	140.686us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	7.000s	142.690us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	97.327us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	24.000s	1031.777us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	36570332651573287462116341286849989027188542477813121670421175576820103281757	89	UVM_INFO @ 6826424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	38071852946352959794136245669676604394582351046746121363132366483780700894043	137	UVM_INFO @ 26570243144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	i2c_target_intr_stress_wr	27046563522938639492886176873758838510814952310181735026787613772342183986380	None
	i2c_target_stress_all	107613447572337920701377727794887404520599637029073013355421777415743430091140	None
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	1046275348887289261266075675879486028164202059179711296103588590659171153183	93	UVM_INFO @ 142690291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	39258909267584773318526407657832221362988348236692118448240940321974503181608	102	UVM_INFO @ 1031777209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	50151978093648654965180556433575172229016410670164956951869717783950090138894	93	UVM_INFO @ 1373758661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	84086932955290017520682855580964105597109674898298276400579553232101172075253	87	UVM_INFO @ 97327163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	41840985874333879903389341471006149339170622155126349460282105004863622483722	88	UVM_INFO @ 10076368921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---