Simulation Results: lc_ctrl/volatile_unlock_disabled

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.76 %
  • code
  • 92.64 %
  • assert
  • 96.83 %
  • func
  • 85.81 %
  • block
  • 96.52 %
  • line
  • 97.20 %
  • branch
  • 91.15 %
  • toggle
  • 86.99 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
96.67%
V2S
90.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.000s 155.683us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.198us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 15.859us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 204.763us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 69.474us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 131.470us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 15.859us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 69.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 316.771us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 1935.607us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 18.249us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 56.749us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 334.758us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_ctrl_prog_failure 2.000s 56.749us 1 1 100.00
lc_ctrl_errors 4.000s 334.758us 1 1 100.00
lc_ctrl_security_escalation 5.000s 357.310us 1 1 100.00
lc_ctrl_jtag_state_failure 20.000s 24208.145us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 4165.782us 1 1 100.00
lc_ctrl_jtag_errors 9.000s 5933.595us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 4.000s 328.901us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.000s 942.480us 0 1 0.00
lc_ctrl_jtag_prog_failure 6.000s 4165.782us 1 1 100.00
lc_ctrl_jtag_errors 9.000s 5933.595us 1 1 100.00
lc_ctrl_jtag_access 4.000s 843.922us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.000s 3259.494us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 773.465us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 133.125us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 10925.702us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 634.372us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 136.339us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 265.038us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 95.999us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 2400.569us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 18.332us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 52.000s 23128.198us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 34.100us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 285.630us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 285.630us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.198us 1 1 100.00
lc_ctrl_csr_rw 1.000s 15.859us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 69.474us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 40.183us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.198us 1 1 100.00
lc_ctrl_csr_rw 1.000s 15.859us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 69.474us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 40.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 928.539us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 189.959us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 189.959us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 1935.607us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_ctrl_sec_cm 3.000s 928.539us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_ctrl_sec_cm 3.000s 928.539us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_ctrl_sec_cm 3.000s 928.539us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_ctrl_sec_cm 3.000s 928.539us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_ctrl_sec_cm 3.000s 928.539us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_ctrl_sec_cm 3.000s 928.539us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_ctrl_sec_cm 3.000s 928.539us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 1288.239us 1 1 100.00
lc_ctrl_sec_cm 3.000s 928.539us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 357.310us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 2.000s 316.771us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.000s 942.480us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 186.267us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 186.267us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 483.408us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 513.168us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 513.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 10.000s 4708.265us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_post_trans 52108519449589900685069264923984989307976359363663432233997936109255902667920 178
UVM_INFO @ 942479710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 96329807450620363116985919156783811340217431041561467698683166478673029182238 673
UVM_INFO @ 4708264927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---