Simulation Results: lc_ctrl/volatile_unlock_enabled

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.11 %
  • code
  • 93.92 %
  • assert
  • 96.69 %
  • func
  • 88.71 %
  • block
  • 97.07 %
  • line
  • 97.63 %
  • branch
  • 92.56 %
  • toggle
  • 87.88 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 260.846us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 17.478us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.911us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 65.649us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 23.147us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 15.758us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 14.911us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 23.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 265.615us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 204.108us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 68.432us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.000s 118.260us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 1622.731us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_ctrl_prog_failure 1.000s 118.260us 1 1 100.00
lc_ctrl_errors 5.000s 1622.731us 1 1 100.00
lc_ctrl_security_escalation 5.000s 439.755us 1 1 100.00
lc_ctrl_jtag_state_failure 14.000s 1507.911us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 73.633us 1 1 100.00
lc_ctrl_jtag_errors 13.000s 4014.370us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 1207.059us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 1483.463us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 73.633us 1 1 100.00
lc_ctrl_jtag_errors 13.000s 4014.370us 1 1 100.00
lc_ctrl_jtag_access 6.000s 570.129us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.000s 5519.560us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 68.686us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 239.300us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.000s 1432.587us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 2330.560us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 94.744us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 325.945us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 53.192us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 400.425us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 15.053us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 69.000s 10127.698us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 23.374us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 57.651us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 57.651us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.478us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.911us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 23.147us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 114.585us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.478us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.911us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 23.147us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 114.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 2145.938us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 2014.530us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 2014.530us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 204.108us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2145.938us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2145.938us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2145.938us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2145.938us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2145.938us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2145.938us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2145.938us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 844.191us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2145.938us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 439.755us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 265.615us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 1483.463us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 695.204us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 695.204us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 2346.180us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1471.492us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1471.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 30.000s 5497.425us 1 1 100.00