Simulation Results: mbx

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.54 %
  • code
  • 87.88 %
  • assert
  • 97.43 %
  • func
  • 74.32 %
  • block
  • 94.47 %
  • line
  • 94.44 %
  • branch
  • 85.05 %
  • toggle
  • 84.15 %
Validation stages
V1
83.33%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 18.000s 1684.639us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 87.206us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 47.862us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 5.000s 1540.773us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 75.631us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 5.551us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 47.862us 1 1 100.00
mbx_csr_aliasing 2.000s 75.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 1.000s 26.698us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 2.000s 11.466us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 16.000s 5797.111us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 764.489us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 37.708us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 49.884us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 5.895us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 5.895us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 87.206us 1 1 100.00
mbx_csr_rw 1.000s 47.862us 1 1 100.00
mbx_csr_aliasing 2.000s 75.631us 1 1 100.00
mbx_same_csr_outstanding 1.000s 34.814us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 87.206us 1 1 100.00
mbx_csr_rw 1.000s 47.862us 1 1 100.00
mbx_csr_aliasing 2.000s 75.631us 1 1 100.00
mbx_same_csr_outstanding 1.000s 34.814us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 171.025us 1 1 100.00
mbx_sec_cm 1.000s 34.570us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 2 test runs
mbx_stress_zero_delays 95206832119144370000048811931903957134719278389855895656802896220173855372736 89
UVM_INFO @ 11466294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_imbx_oob 32449857609387144911418964420522058942728216745254069841863824574139060178249 170
UVM_INFO @ 5797111098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:622) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 114902224343002130985685403497613707575984556842902839459873475240011210670158 85
TL item was: req: (cip_tl_seq_item@17281) { a_addr: 'h8c6de7f4 a_data: 'hd7814409 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'hb7 a_opcode: 'h0 a_user: 'h2589a d_param: 'h0 d_source: 'hb7 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 5894766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 92812951721590951382082224882630806699029552263294458005539490672070357134827 86
TL item was: req: (cip_tl_seq_item@17370) { a_addr: 'h33c15494 a_data: 'h8ada9683 a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'h60 a_opcode: 'h0 a_user: 'h26f86 d_param: 'h0 d_source: 'h60 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 5550958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress 93389037640783348652210147764459617696490980545277375621498387686199634324432 263
UVM_INFO @ 26697927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---