Simulation Results: otbn

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.51 %
  • code
  • 81.82 %
  • assert
  • 89.69 %
  • func
  • 97.03 %
  • block
  • 97.75 %
  • line
  • 97.94 %
  • branch
  • 81.92 %
  • toggle
  • 81.21 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 39.382us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 15.907us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 18.199us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 28.381us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 189.044us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 6.000s 25.362us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 443.671us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 28.381us 1 1 100.00
otbn_csr_aliasing 6.000s 25.362us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 99.000s 23163.057us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 28.000s 671.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 48.000s 200.969us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 62.000s 317.541us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 74.000s 308.277us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 89.000s 517.377us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 11.000s 24.405us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.698us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 59.948us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 16.850us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 20.500us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 110.860us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 110.860us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 18.199us 1 1 100.00
otbn_csr_rw 3.000s 28.381us 1 1 100.00
otbn_csr_aliasing 6.000s 25.362us 1 1 100.00
otbn_same_csr_outstanding 5.000s 87.256us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 18.199us 1 1 100.00
otbn_csr_rw 3.000s 28.381us 1 1 100.00
otbn_csr_aliasing 6.000s 25.362us 1 1 100.00
otbn_same_csr_outstanding 5.000s 87.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 98.039us 1 1 100.00
otbn_dmem_err 13.000s 78.498us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 7.000s 26.129us 1 1 100.00
otbn_controller_ispr_rdata_err 11.000s 60.228us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 204.450us 1 1 100.00
otbn_urnd_err 9.000s 70.682us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 7.000s 30.386us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 34.251us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 26.232us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
otbn_tl_intg_err 12.000s 883.416us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 45.000s 169.293us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 39.382us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 13.000s 78.498us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 98.039us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 12.000s 883.416us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 24.405us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 98.039us 1 1 100.00
otbn_dmem_err 13.000s 78.498us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.698us 1 1 100.00
otbn_illegal_mem_acc 7.000s 30.386us 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 15.907us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 98.039us 1 1 100.00
otbn_dmem_err 13.000s 78.498us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.698us 1 1 100.00
otbn_illegal_mem_acc 7.000s 30.386us 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 24.405us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 98.039us 1 1 100.00
otbn_dmem_err 13.000s 78.498us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.698us 1 1 100.00
otbn_illegal_mem_acc 7.000s 30.386us 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 15.907us 1 1 100.00
sec_cm_ctrl_redun 0 1 0.00
otbn_ctrl_redun 5.000s 18.026us 0 1 0.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 25.152us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 37.000s 413.129us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 37.000s 413.129us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 37.654us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 11.000s 217.847us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 63.393us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 63.393us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 7.000s 19.996us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 15.907us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 15.907us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 15.907us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 74.000s 308.277us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 15.907us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 15.907us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 85.702us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 15.907us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 317.000s 6336.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 232.000s 4589.240us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 10.000s 29.251us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 2752462013647752622068379556831828030279368364352160028747537356728340674703 259
UVM_INFO @ 4589239949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_controller.sv,726): Assertion NoStallOnBranch has failed 1 test run
otbn_ctrl_redun 12000424099772814058273027586317064539390268278006776076697453648795292557310 109
UVM_ERROR @ 18025688 ps: (otbn_controller.sv:726) [ASSERT FAILED] NoStallOnBranch
UVM_INFO @ 18025688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---